Hi Marc, On Tue, Dec 4, 2018 at 6:10 PM Marc Gonzalez <marc.w.gonzalez@xxxxxxx> wrote: > > On 04/12/2018 12:01, Vivek Gautam wrote: > > > Qualcomm SoCs have an additional level of cache called as > > System cache, aka. Last level cache (LLC). This cache sits right > > before the DDR, and is tightly coupled with the memory controller. > > The cache is available to all the clients present in the SoC system. > > The clients request their slices from this system cache, make it > > active, and can then start using it. > > For these clients with smmu, to start using the system cache for > > buffers and, related page tables [1], memory attributes need to be > > set accordingly. > > This change updates the MAIR and TCR configurations with correct > > attributes to use this system cache. > > This is version 2 of the patch, right? > > Version 1 would have been: > https://lkml.org/lkml/2018/6/15/186 That's right, this is version 2 of the patch. My bad, I noticed it after sending the patch. But i thought of not spamming about it, and thought of conveying it in the first response to any comments I get. Thanks for bringing it up. Best regards Vivek > > Regards. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
