On Thu, Nov 29, 2018 at 12:24 PM Tomasz Figa <tfiga@xxxxxxxxxxxx> wrote: > > [CC Marek] > > On Thu, Nov 29, 2018 at 9:09 AM Daniel Vetter <daniel@xxxxxxxx> wrote: > > > > On Thu, Nov 29, 2018 at 5:57 PM Christoph Hellwig <hch@xxxxxx> wrote: > > > > > > Note that one thing I'd like to avoid is exposing these funtions directly > > > to drivers, as that will get us into all kinds of abuses. > > > > What kind of abuse do you expect? It could very well be that gpu folks > > call that "standard use case" ... At least on x86 with the i915 driver > > we pretty much rely on architectural guarantees for how cache flushes > > work very much. Down to userspace doing the cache flushing for > > mappings the kernel has set up. > > i915 is a very specific case of a fully contained, > architecture-specific hardware subsystem, where you can just hardcode > all integration details inside the driver, because nobody else would > care. > > In ARM world, you can have the same IP blocks licensed by multiple SoC > vendors with different integration details and that often includes the > option of coherency. fwiw, I believe all the GPU IP blocks that are used across multiple SoCs have their own GPU MMU (potentially in addition to an iommu?). So the dma-api is a much better fit for them.. drm/msm is a lot closer to drm/i915 scenario, so I don't so much care if the solution to our unique problem isn't something that would work for other drivers ;-) BR, -R
