Quoting Loic Poulain (2018-11-20 03:14:56)
> Add SPI friendly clock rates to the spi freq table.
> Today it's not possible to use SPI at lower than 960Khz.
> This patch adds 100/250/500/1000 khz configs to the table.
s/khz/kHz/
>
> Signed-off-by: Loic Poulain <loic.poulain@xxxxxxxxxx>
> ---
> drivers/clk/qcom/gcc-msm8916.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
> index ac2b0aa..7d9647c 100644
> --- a/drivers/clk/qcom/gcc-msm8916.c
> +++ b/drivers/clk/qcom/gcc-msm8916.c
> @@ -544,7 +544,11 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> };
>
> static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
> + F(100000, P_XO, 16, 2, 24),
> + F(250000, P_XO, 16, 5, 24),
> + F(500000, P_XO, 8, 5, 24),
> F(960000, P_XO, 10, 1, 2),
> + F(1000000, P_XO, 4, 5, 24),
Does Qualcomm have information on these rates? Have they been tested?
And did you measure these frequencies? The math checks out, but I wonder
if the hardware can actually do it.
