[PATCH] rnndb: Add additional a6xx registers in gpu CX

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Add a few additional registers in the CX domain needed to implement
system cache support for a6xx.
---
 rnndb/adreno/a6xx.xml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml
index b2bd64b..78ba1ce 100644
--- a/rnndb/adreno/a6xx.xml
+++ b/rnndb/adreno/a6xx.xml
@@ -2963,4 +2963,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
 </domain>
 
+<domain name="A6XX_CX_MISC" width="32">
+	<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
+	<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
+</domain>
+
 </database>
-- 
1.9.1




[Index of Archives]     [Linux ARM Kernel]     [Linux ARM]     [Linux Omap]     [Fedora ARM]     [Linux for Sparc]     [IETF Annouce]     [Security]     [Bugtraq]     [Linux MIPS]     [ECOS]     [Asterisk Internet PBX]     [Linux API]

  Powered by Linux