On Fri, Oct 05, 2018 at 06:38:32PM +0530, Sharat Masetty wrote: > Add the registers needed for configuring the system cache slice info and > other parameters in the GPU. This would conflict with msm-next or at least with the latest update from the rnndb. It is good to have this out here for people to prototype but we need to do a better job of keeping rnndb up to date so please send out a update for that as soon as you can - it is a pretty easy thing for Rob to generate and push new headers if we know that the database is good. Jordan > Signed-off-by: Sharat Masetty <smasetty@xxxxxxxxxxxxxx> > --- > drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h > index 2206765..2645b8f 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h > @@ -1780,5 +1780,8 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) > > #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 > > +#define REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 > + > +#define REG_A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 > > #endif /* A6XX_XML */ > -- > 1.9.1 > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
