Re: [PATCH] drm/msm: dpu: Add tracing around CTL_FLUSH

[Abhinav Kumar <abhinavk@xxxxxxxxxxxxxx>]

On 2018-10-03 18:36, Sean Paul wrote:
> From: Sean Paul <seanpaul@xxxxxxxxxxxx>
>
> I found these tracepoints useful for debugging cursor/ctl, someone else
> might find them useful too
>
> Signed-off-by: Sean Paul <seanpaul@xxxxxxxxxxxx>
Reviewed-by: Abhinav Kumar <abhinavk@xxxxxxxxxxxxxx>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 26 ++++++++----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h  | 47 ++++++++++++++++++++++
>  2 files changed, 65 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index b394a1818c5d..3f50164ad30e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -15,6 +15,7 @@
>  #include "dpu_hw_ctl.h"
>  #include "dpu_dbg.h"
>  #include "dpu_kms.h"
> +#include "dpu_trace.h"
>
>  #define   CTL_LAYER(lm)                 \
>  	(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
> @@ -72,24 +73,39 @@ static int _mixer_stages(const struct dpu_lm_cfg
> *mixer, int count,
>  	return stages;
>  }
>
> +static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl 
> *ctx)
> +{
> +	struct dpu_hw_blk_reg_map *c = &ctx->hw;
> +
> +	return DPU_REG_READ(c, CTL_FLUSH);
> +}
> +
>  static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx)
>  {
> +	trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask,
> +				       dpu_hw_ctl_get_flush_register(ctx));
>  	DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
>  }
>
>  static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
>  {
> +	trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask,
> +					 dpu_hw_ctl_get_flush_register(ctx));
>  	DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
>  }
>
>  static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl 
> *ctx)
>  {
> +	trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
> +				     dpu_hw_ctl_get_flush_register(ctx));
>  	ctx->pending_flush_mask = 0x0;
>  }
>
>  static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl 
> *ctx,
>  		u32 flushbits)
>  {
> +	trace_dpu_hw_ctl_update_pending_flush(flushbits,
> +					      ctx->pending_flush_mask);
>  	ctx->pending_flush_mask |= flushbits;
>  }
>
> @@ -103,17 +119,11 @@ static u32 dpu_hw_ctl_get_pending_flush(struct
> dpu_hw_ctl *ctx)
>
>  static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
>  {
> -
> +	trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask,
> +				     dpu_hw_ctl_get_flush_register(ctx));
>  	DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
>  }
>
> -static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl 
> *ctx)
> -{
> -	struct dpu_hw_blk_reg_map *c = &ctx->hw;
> -
> -	return DPU_REG_READ(c, CTL_FLUSH);
> -}
> -
>  static inline uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl 
> *ctx,
>  	enum dpu_sspp sspp)
>  {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> index e12c4cefb742..636b31b0d311 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> @@ -1004,6 +1004,53 @@ TRACE_EVENT(dpu_core_perf_update_clk,
>  		  __entry->stop_req ? "true" : "false", __entry->clk_rate)
>  );
>
> +TRACE_EVENT(dpu_hw_ctl_update_pending_flush,
> +	TP_PROTO(u32 new_bits, u32 pending_mask),
> +	TP_ARGS(new_bits, pending_mask),
> +	TP_STRUCT__entry(
> +		__field(	u32,			new_bits	)
> +		__field(	u32,			pending_mask	)
> +	),
> +	TP_fast_assign(
> +		__entry->new_bits = new_bits;
> +		__entry->pending_mask = pending_mask;
> +	),
> +	TP_printk("new=%x existing=%x", __entry->new_bits,
> +		  __entry->pending_mask)
> +);
> +
> +DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template,
> +	TP_PROTO(u32 pending_mask, u32 ctl_flush),
> +	TP_ARGS(pending_mask, ctl_flush),
> +	TP_STRUCT__entry(
> +		__field(	u32,			pending_mask	)
> +		__field(	u32,			ctl_flush	)
> +	),
> +	TP_fast_assign(
> +		__entry->pending_mask = pending_mask;
> +		__entry->ctl_flush = ctl_flush;
> +	),
> +	TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask,
> +		  __entry->ctl_flush)
> +);
> +DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, 
> dpu_hw_ctl_clear_pending_flush,
> +	TP_PROTO(u32 pending_mask, u32 ctl_flush),
> +	TP_ARGS(pending_mask, ctl_flush)
> +);
> +DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
> +	     dpu_hw_ctl_trigger_pending_flush,
> +	TP_PROTO(u32 pending_mask, u32 ctl_flush),
> +	TP_ARGS(pending_mask, ctl_flush)
> +);
> +DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, 
> dpu_hw_ctl_trigger_prepare,
> +	TP_PROTO(u32 pending_mask, u32 ctl_flush),
> +	TP_ARGS(pending_mask, ctl_flush)
> +);
> +DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, 
> dpu_hw_ctl_trigger_start,
> +	TP_PROTO(u32 pending_mask, u32 ctl_flush),
> +	TP_ARGS(pending_mask, ctl_flush)
> +);
> +
>  #define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, 
> name, 0)
>  #define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, 
> name, 1)
>  #define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)