On Thu, Aug 16, 2018 at 10:49 PM Doug Anderson <dianders@xxxxxxxxxxxx> wrote: > On Thu, Aug 16, 2018 at 1:06 PM, Stephen Boyd <swboyd@xxxxxxxxxxxx> wrote: > > The interrupt controller hardware in this pin controller has two status > > enable bits. The first "normal" status enable bit enables or disables > > the summary interrupt line being raised when a gpio interrupt triggers > > and the "raw" status enable bit allows or prevents the hardware from > > latching an interrupt into the status register for a gpio interrupt. > > Currently we just toggle the "normal" status enable bit in the mask and > > unmask ops so that the summary irq interrupt going to the CPU's > > interrupt controller doesn't trigger for the masked gpio interrupt. > > > > For a level triggered interrupt, the flow would be as follows: the pin > > controller sees the interrupt, latches the status into the status > > register, raises the summary irq to the CPU, summary irq handler runs > > and calls handle_level_irq(), handle_level_irq() masks and acks the gpio > > interrupt, the interrupt handler runs, and finally unmask the interrupt. > > When the interrupt handler completes, we expect that the interrupt line > > level will go back to the deasserted state so the genirq code can unmask > > the interrupt without it triggering again. > > > > If we only mask the interrupt by clearing the "normal" status enable bit > > then we'll ack the interrupt but it will continue to show up as pending > > in the status register because the raw status bit is enabled, the > > hardware hasn't deasserted the line, and thus the asserted state latches > > into the status register again. When the hardware deasserts the > > interrupt the pin controller still thinks there is a pending unserviced > > level interrupt because it latched it earlier. This behavior causes > > software to see an extra interrupt for level type interrupts each time > > the interrupt is handled. > > > > Let's fix this by clearing the raw status enable bit for level type > > interrupts so that the hardware stops latching the status of the > > interrupt after we ack it. We don't do this for edge type interrupts > > because it seems that toggling the raw status enable bit for edge type > > interrupts causes spurious edge interrupts. > > > > Cc: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> > > Cc: Doug Anderson <dianders@xxxxxxxxxxxx> > > Signed-off-by: Stephen Boyd <swboyd@xxxxxxxxxxxx> > > --- > > drivers/pinctrl/qcom/pinctrl-msm.c | 24 ++++++++++++++++++++++++ > > 1 file changed, 24 insertions(+) > > Reviewed-by: Douglas Anderson <dianders@xxxxxxxxxxxx> > > NOTE: IMO we should land this fix even if we continue to have debate > on patch #2 and #3 since this fixes a definite problem. OK makes sense, I guess I'll queue this for fixes once v4.19-rc1 is out. Would be nice to also get Bjorn's buy-in on it! Yours, Linus Walleij
