Fix the following NAND register write errors which will
be generated if access protection is enabled.
1. SFLASHC_BURST_CFG register is not available for supported
NAND contollers by this driver, so this can be removed.
2. NAND_CTRL is operational register and register writes to
operational registers should always be done through
command descriptors if BAM_MODE is already enabled.
With full boot chain, bootloader already enables
BAM_MODE so read the NAND_CTRL register value and write
only if BAM_MODE is not set.
Signed-off-by: Abhishek Sahu <absahu@xxxxxxxxxxxxxx>
---
drivers/mtd/nand/raw/qcom_nandc.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index df12cf3..9e6b383 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2693,15 +2693,20 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
{
u32 nand_ctrl;
- /* kill onenand */
- nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
NAND_DEV_CMD_VLD_VAL);
/* enable ADM or BAM DMA */
if (nandc->props->is_bam) {
nand_ctrl = nandc_read(nandc, NAND_CTRL);
- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+ /*
+ * Once BAM_MODE_EN bit is set then QPIC_NAND_CTRL register
+ * should be written with BAM instead of writel.
+ * Check if BAM_MODE_EN is already set by bootloader and write
+ * only if this bit is not set.
+ */
+ if (!(nand_ctrl & BAM_MODE_EN))
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
} else {
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
}
--
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is a member of Code Aurora Forum, hosted by The Linux Foundation
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