On 2018-07-04 01:18, Sean Paul wrote:
Signed-off-by: Sean Paul <seanpaul@xxxxxxxxxxxx>
Reviewed-by: Rajesh Yadav <ryadav@xxxxxxxxxxxxxx>
---
.../devicetree/bindings/display/msm/dpu.txt | 22 +++++++++++--------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt
b/Documentation/devicetree/bindings/display/msm/dpu.txt
index a4407b848faf..d3b13a517579 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -39,6 +39,7 @@ Required properties:
- reg: physical base address and length of controller's registers.
- reg-names : register region names. The following region is required:
* "mdp_phys"
+ * "vbif_phys"
- clocks: list of phandles for clock device nodes needed by the
device.
- clock-names: device clock names, must be in same order as clocks
property.
The following clocks are required.
@@ -74,15 +75,16 @@ Example:
power-domains = <&clock_dispcc 0>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
- <&gcc GCC_DISP_AXI_CLK>,
- <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
- clock-names = "gcc_iface", "gcc_bus", "core_clk";
+ <&gcc GCC_DISP_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface_clk", "bus_clk", "core_clk";
+ clock-frequency = <0 0 300000000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
- iommus = <&apps_smmu 0>;
+ iommus = <&apps_iommu 0>;
#address-cells = <1>;
#size-cells = <1>;
@@ -90,14 +92,16 @@ Example:
mdss_mdp: mdp@ae01000 {
compatible = "qcom,dpu";
- reg = <0x0ae01000 0x8f000>;
- reg-names = "mdp_phys";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp_phys", "vbif_phys";
clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
- <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
- <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
- <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "iface_clk", "bus_clk", "core_clk", "vsync_clk";
+ clock-frequency = <0 0 300000000 19200000>;
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
--
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