Higher values of pclk can exceed 32 bits when multiplied
by a factor.
Make the pclk_rate u64 to accommodate higher pixel clock
rates.
Signed-off-by: Abhinav Kumar <abhinavk@xxxxxxxxxxxxxx>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index b916f46..4935387 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -668,7 +668,7 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
u8 lanes = msm_host->lanes;
u32 bpp = dsi_get_bpp(msm_host->format);
- u32 pclk_rate;
+ u64 pclk_rate;
if (!mode) {
pr_err("%s: mode not set\n", __func__);
@@ -683,7 +683,7 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
}
- DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
+ DBG("pclk=%llu, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
--
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