On 2018-05-16 10:03, Stephen Boyd wrote:
Quoting Rishabh Bhatnagar (2018-05-08 13:22:00)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
new file mode 100644
index 0000000..a586a17
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -0,0 +1,32 @@
+== Introduction==
+
+LLCC (Last Level Cache Controller) provides last level of cache
memory in SOC,
+that can be shared by multiple clients. Clients here are different
cores in the
+SOC, the idea is to minimize the local caches at the clients and
migrate to
+common pool of memory. Cache memory is divided into partitions called
slices
+which are assigned to clients. Clients can query the slice details,
activate
+and deactivate them.
+
+Properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sdm845-llcc"
+
+- reg:
+ Usage: required
+ Value Type: <prop-encoded-array>
+ Definition: Start address and the range of the LLCC registers.
Start address and size?
Yes i'll change it to Start address and size of the register region.
+
+- max-slices:
+ usage: required
+ Value Type: <u32>
+ Definition: Number of cache slices supported by hardware
+
+Example:
+
+ llcc: qcom,llcc@1100000 {
cache-controller@1100000 ?
We have tried to use consistent naming convention as in llcc_*
everywhere.
Using cache-controller will mix and match the naming convention. Also in
the documentation it is explained what llcc is and its full form.
+ compatible = "qcom,sdm845-llcc";
+ reg = <0x1100000 0x250000>;
+ max-slices = <32>;
+ };
--
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