Re: [DPU PATCH 02/11] drm/msm/mdp5: subclass msm_mdss for mdp5

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On Thu, May 10, 2018 at 01:59:36PM +0530, Rajesh Yadav wrote:
> SoCs having mdp5 or dpu have identical tree like
> device hierarchy where MDSS top level wrapper manages
> common power resources for all child devices.
> 
> Subclass msm_mdss so that msm_mdss includes common defines
> and mdp5/dpu mdss derivations to include any extensions.
> 
> Add mdss helper interface (msm_mdss_funcs) to msm_mdss
> base for mdp5/dpu mdss specific implementation calls.
> 
> This change subclasses msm_mdss for mdp5, dpu specific
> changes will be done separately.
> 
> Signed-off-by: Rajesh Yadav <ryadav@xxxxxxxxxxxxxx>

Hi Rajesh,
Thanks for the patch, everything looks good to me aside from one tiny indent
fix. With that resolved, please add my

Reviewed-by: Sean Paul <seanpaul@xxxxxxxxxxxx>

> ---
>  drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 154 ++++++++++++++++--------------
>  drivers/gpu/drm/msm/msm_drv.c             |  23 +++--
>  drivers/gpu/drm/msm/msm_kms.h             |  20 ++--
>  3 files changed, 110 insertions(+), 87 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
> index f2a0db7..88190e3 100644
> --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
> +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c

<snip />

> -static int mdss_irq_domain_init(struct msm_mdss *mdss)
> +static int mdss_irq_domain_init(struct mdp5_mdss *mdp5_mdss)
>  {
> -	struct device *dev = mdss->dev->dev;
> +	struct device *dev = mdp5_mdss->base.dev->dev;
>  	struct irq_domain *d;
>  
>  	d = irq_domain_add_linear(dev->of_node, 32, &mdss_hw_irqdomain_ops,
> -				  mdss);
> +			mdp5_mdss);

nit: indent change here

>  	if (!d) {
>  		dev_err(dev, "mdss irq domain add failed\n");
>  		return -ENXIO;
>  	}
>  
> -	mdss->irqcontroller.enabled_mask = 0;
> -	mdss->irqcontroller.domain = d;
> +	mdp5_mdss->irqcontroller.enabled_mask = 0;
> +	mdp5_mdss->irqcontroller.domain = d;
>  
>  	return 0;
>  }
>  

<snip />

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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