Quoting Taniya Das (2018-05-02 03:51:17)
> +
> +static DEFINE_MUTEX(rpmh_clk_lock);
> +
> +#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
> + _res_en_offset, _res_on) \
> + static struct clk_rpmh _platform##_##_name_active; \
> + static struct clk_rpmh _platform##_##_name = { \
> + .res_name = _res_name, \
> + .res_addr = _res_en_offset, \
> + .res_on_val = _res_on, \
> + .peer = &_platform##_##_name_active, \
> + .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
> + BIT(RPMH_ACTIVE_ONLY_STATE) | \
> + BIT(RPMH_SLEEP_STATE)), \
> + .hw.init = &(struct clk_init_data){ \
> + .ops = &clk_rpmh_ops, \
> + .name = #_name, \
> + .parent_names = (const char *[]){ "xo_board", \
> + "xo_board_div" }, \
The rpmh clks that do a div 2 can have a recalc_rate function that
returns the xo_board clk rate divided by 2 all the time. That may be
easier to do. Keep xo_board as parent, but then specify if it does div-2
or div-1 in the SoC specific listing. Then DT can only show 38.4 MHz.
The div 2 part is inside the SoC anyway so this seems more accurate too.
> + .num_parents = 2, \
> + }, \
> + }; \
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