On 3/23/2018 2:25 PM, Alexander Duyck wrote: >> + /* We need this if more than one processor can write to our tail >> + * at a time, it synchronizes IO on IA64/Altix systems >> + */ >> + mmiowb(); >> } > The mmiowb shouldn't be needed for Rx. Only one CPU will be running > NAPI for the queue and we will synchronize this with a full writel > anyway when we re-enable the interrupts. > OK. I can fix this on the next version. I did a blanket search and replace for my writel_relaxed() changes as I don't know the code well enough. Please point me to the redundant ones. -- Sinan Kaya Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
