Quoting Robin Murphy (2018-03-19 11:16:15) > On 19/03/18 16:57, Stephen Boyd wrote: > [...] > >> + > > > >> + writel_relaxed(SSSCTL_VAL, vbases[APC_BASE] + > >> + PWRCL_REG_OFFSET + SSSCTL_OFFSET); > >> + /* Ensure SSSCTL config goes through before enabling ACD. */ > >> + mb(); > > > > Use writel instead. > > Note that writel() only gives an implicit wmb() *before* the store to > ensure ordering against any previous writes. If this code really needs > to ensure that the given write has definitely completed before any other > accesses happen, then it still needs an explicit barrier *after* the > write*(), unless perhaps the next access is always guaranteed to be a > non-relaxed write (thus implicitly providing a suitable DSB). > Ah right. So this should be a wmb() too? I suspect it's to order with the write to the l2 indirect registers, but reading that register before the MMIO write is not a problem. The comment above the l2 accessors could be slightly more specific here and it would help immensely. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
