On Wed, Feb 21, 2018 at 4:42 PM, Sean Paul <seanpaul@xxxxxxxxxxxx> wrote:
> We need to have a discussion about how to introduce this in a way that
> it can be leveraged by other platforms/userspaces. For now, remove
> support since we don't need it yet.
>
> Signed-off-by: Sean Paul <seanpaul@xxxxxxxxxxxx>
Agreed..
Reviewed-by: Rob Clark <robdclark@xxxxxxxxx>
> ---
> drivers/gpu/drm/drm_framebuffer.c | 3 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 -------
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 43 -------------------
> .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 -----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h | 2 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 -------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 21 +++------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 3 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 +---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 15 -------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 41 +-----------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c | 10 -----
> drivers/gpu/drm/msm/msm_drv.h | 3 --
> include/uapi/drm/dpu_drm.h | 42 ------------------
> include/uapi/drm/drm_mode.h | 1 -
> 18 files changed, 9 insertions(+), 243 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c
> index 8222ff7d3e93..5a13ff29f4f0 100644
> --- a/drivers/gpu/drm/drm_framebuffer.c
> +++ b/drivers/gpu/drm/drm_framebuffer.c
> @@ -268,8 +268,7 @@ drm_internal_framebuffer_create(struct drm_device *dev,
> struct drm_framebuffer *fb;
> int ret;
>
> - if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS |
> - DRM_MODE_FB_SECURE)) {
> + if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS)) {
> DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
> return ERR_PTR(-EINVAL);
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index df6cbeb15cf5..3cdf1e3d9d96 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -39,13 +39,6 @@
> #include "dpu_core_perf.h"
> #include "dpu_trace.h"
>
> -/* defines for secure channel call */
> -#define SEC_SID_CNT 2
> -#define SEC_SID_MASK_0 0x80881
> -#define SEC_SID_MASK_1 0x80C81
> -#define MEM_PROTECT_SD_CTRL_SWITCH 0x18
> -#define MDP_DEVICE_ID 0x1A
> -
> struct dpu_crtc_irq_info {
> struct dpu_irq_callback irq;
> u32 event;
> @@ -3994,10 +3987,6 @@ static void dpu_crtc_install_properties(struct drm_crtc *crtc,
> struct drm_device *dev;
> struct dpu_kms_info *info;
> struct dpu_kms *dpu_kms;
> - static const struct drm_prop_enum_list e_secure_level[] = {
> - {DPU_DRM_SEC_NON_SEC, "sec_and_non_sec"},
> - {DPU_DRM_SEC_ONLY, "sec_only"},
> - };
>
> DPU_DEBUG("\n");
>
> @@ -4080,11 +4069,6 @@ static void dpu_crtc_install_properties(struct drm_crtc *crtc,
> msm_property_install_volatile_range(&dpu_crtc->property_info,
> "dpu_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1);
>
> - msm_property_install_enum(&dpu_crtc->property_info, "security_level",
> - 0x0, 0, e_secure_level,
> - ARRAY_SIZE(e_secure_level),
> - CRTC_PROP_SECURITY_LEVEL);
> -
> dpu_kms_info_reset(info);
>
> if (catalog->has_dim_layer) {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 17d21fff3f0a..b63df243be33 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -51,20 +51,14 @@ enum dpu_crtc_client_type {
> * enum dpu_crtc_smmu_state: smmu state
> * @ATTACHED: all the context banks are attached.
> * @DETACHED: all the context banks are detached.
> - * @DETACHED_SEC: secure context bank is detached.
> * @ATTACH_ALL_REQ: transient state of attaching context banks.
> * @DETACH_ALL_REQ: transient state of detaching context banks.
> - * @DETACH_SEC_REQ: tranisent state of secure context bank is detached
> - * @ATTACH_SEC_REQ: transient state of attaching secure context bank.
> */
> enum dpu_crtc_smmu_state {
> ATTACHED = 0,
> DETACHED,
> - DETACHED_SEC,
> ATTACH_ALL_REQ,
> DETACH_ALL_REQ,
> - DETACH_SEC_REQ,
> - ATTACH_SEC_REQ,
> };
>
> /**
> @@ -621,41 +615,4 @@ void dpu_crtc_res_put(struct drm_crtc_state *state, u32 type, u64 tag);
> void dpu_crtc_get_crtc_roi(struct drm_crtc_state *state,
> const struct dpu_rect **crtc_roi);
>
> -/** dpu_crt_get_secure_level - retrieve the secure level from the give state
> - * object, this is used to determine the secure state of the crtc
> - * @crtc : Pointer to drm crtc structure
> - * @usr: Pointer to drm crtc state
> - * return: secure_level
> - */
> -static inline int dpu_crtc_get_secure_level(struct drm_crtc *crtc,
> - struct drm_crtc_state *state)
> -{
> - if (!crtc || !state)
> - return -EINVAL;
> -
> - return dpu_crtc_get_property(to_dpu_crtc_state(state),
> - CRTC_PROP_SECURITY_LEVEL);
> -}
> -
> -/**
> - * dpu_crtc_get_secure_transition - determines the operations to be
> - * performed before transitioning to secure state
> - * This function should be called after swapping the new state
> - * @crtc: Pointer to drm crtc structure
> - * @old_crtc_state: Poniter to previous CRTC state
> - * Returns the bitmask of operations need to be performed, -Error in
> - * case of error cases
> - */
> -int dpu_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
> - struct drm_crtc_state *old_crtc_state,
> - bool old_valid_fb);
> -
> -/**
> - * dpu_crtc_secure_ctrl - Initiates the transition between secure and
> - * non-secure world
> - * @crtc: Pointer to crtc
> - * @post_commit: if this operation is triggered after commit
> - */
> -int dpu_crtc_secure_ctrl(struct drm_crtc *crtc, bool post_commit);
> -
> #endif /* _DPU_CRTC_H_ */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> index 75255fc42e7e..9a6fa3e1e8b4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> @@ -279,19 +279,8 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
>
> wb_cfg->intf_mode = phys_enc->intf_mode;
>
> - fb_mode = dpu_connector_get_property(phys_enc->connector->state,
> - CONNECTOR_PROP_FB_TRANSLATION_MODE);
> - if (phys_enc->enable_state == DPU_ENC_DISABLING)
> - wb_cfg->is_secure = false;
> - else if (fb_mode == DPU_DRM_FB_SEC)
> - wb_cfg->is_secure = true;
> - else
> - wb_cfg->is_secure = false;
> -
> aspace = phys_enc->dpu_kms->base.aspace;
>
> - DPU_DEBUG("[fb_secure:%d]\n", wb_cfg->is_secure);
> -
> ret = msm_framebuffer_prepare(fb, aspace);
> if (ret) {
> DPU_ERROR("prep fb failed, %d\n", ret);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c
> index 6b560f1c0fce..b20a64037666 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c
> @@ -606,7 +606,6 @@ static int dpu_hw_rot_commit(struct dpu_hw_rot *hw, struct dpu_hw_rot_cmd *data,
> rot_cmd.hflip = data->rot90 ? !data->hflip : data->hflip;
> rot_cmd.vflip = data->rot90 ? !data->vflip : data->vflip;
>
> - rot_cmd.secure = data->secure;
> rot_cmd.clkrate = data->clkrate;
> rot_cmd.data_bw = 0;
> rot_cmd.prefill_bw = data->prefill_bw;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h
> index f72d9c06b557..df15ed5f102f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h
> @@ -44,7 +44,6 @@ enum dpu_hw_rot_cmd_type {
> * @rot90: true if rotation 90 in counter clockwise is required
> * @hflip: true if horizontal flip is required prior to rotation
> * @vflip: true if vertical flip is required prior to rotation
> - * @secure: true if image content is in secure domain
> * @video_mode: true if rotator is feeding into video interface
> * @clkrate : clock rate in Hz
> * @prefill_bw: prefill bandwidth in Bps (video mode only)
> @@ -80,7 +79,6 @@ struct dpu_hw_rot_cmd {
> bool rot90;
> bool hflip;
> bool vflip;
> - bool secure;
> bool video_mode;
> u64 clkrate;
> u64 prefill_bw;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 705b4510b730..3fecf33a164d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -360,35 +360,6 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
> }
>
> -static void dpu_hw_sspp_setup_secure(struct dpu_hw_pipe *ctx,
> - enum dpu_sspp_multirect_index rect_mode,
> - bool enable)
> -{
> - struct dpu_hw_blk_reg_map *c;
> - u32 secure = 0, secure_bit_mask;
> - u32 idx;
> -
> - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
> - return;
> -
> - c = &ctx->hw;
> -
> - if (enable) {
> - if ((rect_mode == DPU_SSPP_RECT_SOLO)
> - || (rect_mode == DPU_SSPP_RECT_0))
> - secure_bit_mask =
> - (rect_mode == DPU_SSPP_RECT_SOLO) ? 0xF : 0x5;
> - else
> - secure_bit_mask = 0xA;
> -
> - secure = DPU_REG_READ(c, SSPP_SRC_ADDR_SW_STATUS + idx);
> - secure |= secure_bit_mask;
> - }
> -
> - DPU_REG_WRITE(c, SSPP_SRC_ADDR_SW_STATUS + idx, secure);
> -}
> -
> -
> static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx,
> struct dpu_hw_pixel_ext *pe_ext)
> {
> @@ -910,7 +881,6 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
> c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress;
> c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill;
> c->ops.setup_pe = dpu_hw_sspp_setup_pe_config;
> - c->ops.setup_secure_address = dpu_hw_sspp_setup_secure;
> }
>
> if (test_bit(DPU_SSPP_EXCL_RECT, &features))
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index 23f37040acaa..de971f17f130 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -25,12 +25,11 @@ struct dpu_hw_pipe;
> /**
> * Flags
> */
> -#define DPU_SSPP_SECURE_OVERLAY_SESSION 0x1
> -#define DPU_SSPP_FLIP_LR 0x2
> -#define DPU_SSPP_FLIP_UD 0x4
> -#define DPU_SSPP_SOURCE_ROTATED_90 0x8
> -#define DPU_SSPP_ROT_90 0x10
> -#define DPU_SSPP_SOLID_FILL 0x20
> +#define DPU_SSPP_FLIP_LR BIT(0)
> +#define DPU_SSPP_FLIP_UD BIT(1)
> +#define DPU_SSPP_SOURCE_ROTATED_90 BIT(2)
> +#define DPU_SSPP_ROT_90 BIT(3)
> +#define DPU_SSPP_SOLID_FILL BIT(4)
>
> /**
> * Define all scaler feature bits in catalog
> @@ -505,16 +504,6 @@ struct dpu_hw_sspp_ops {
> */
> void (*setup_cdp)(struct dpu_hw_pipe *ctx,
> struct dpu_hw_pipe_cdp_cfg *cfg);
> -
> - /**
> - * setup_secure_address - setup secureity status of the source address
> - * @ctx: Pointer to pipe context
> - * @index: rectangle index in multirect
> - * @enable: enable content protected buffer state
> - */
> - void (*setup_secure_address)(struct dpu_hw_pipe *ctx,
> - enum dpu_sspp_multirect_index index,
> - bool enable);
> };
>
> /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> index a07c30528096..fb02df4209c6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> @@ -153,9 +153,6 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
> (ctx->mdp->highest_bank_bit << 4));
> }
>
> - if (data->is_secure)
> - dst_addr_sw |= BIT(0);
> -
> DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF);
> DPU_REG_WRITE(c, WB_DST_FORMAT, dst_format);
> DPU_REG_WRITE(c, WB_DST_OP_MODE, opmode);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
> index 822a4c57b369..145ebbc87b58 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
> @@ -25,7 +25,6 @@ struct dpu_hw_wb_cfg {
> enum dpu_intf_mode intf_mode;
> struct traffic_shaper_cfg ts_cfg;
> struct dpu_rect roi;
> - bool is_secure;
> };
>
> /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index b919c9a6a463..81fd3a429e9f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1236,14 +1236,10 @@ struct dpu_kms_fbo *dpu_kms_fbo_alloc(struct drm_device *dev, u32 width,
> /* allocate backing buffer object */
> if (dpu_kms->iclient) {
> #ifdef CONFIG_ION
> - u32 heap_id = fbo->flags & DRM_MODE_FB_SECURE ?
> - ION_HEAP(ION_SECURE_HEAP_ID) :
> - ION_HEAP(ION_SYSTEM_HEAP_ID);
> - u32 iflags = fbo->flags & DRM_MODE_FB_SECURE ?
> - (ION_FLAG_SECURE | ION_FLAG_CP_PIXEL) : 0;
> + u32 heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID);
>
> fbo->ihandle = ion_alloc(dpu_kms->iclient,
> - fbo->layout.total_size, SZ_4K, heap_id, iflags);
> + fbo->layout.total_size, SZ_4K, heap_id, 0);
> if (IS_ERR_OR_NULL(fbo->ihandle)) {
> DPU_ERROR("failed to alloc ion memory\n");
> ret = PTR_ERR(fbo->ihandle);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> index dea49f3d42b4..8cadd29a48b1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> @@ -93,21 +93,6 @@
> /* timeout in frames waiting for frame done */
> #define DPU_FRAME_DONE_TIMEOUT 60
>
> -/* max active secure client counts allowed */
> -#define MAX_ALLOWED_SECURE_CLIENT_CNT 1
> -
> -/* max active crtc when secure client is active */
> -#define MAX_ALLOWED_CRTC_CNT_DURING_SECURE 1
> -
> -/* max virtual encoders per secure crtc */
> -#define MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC 1
> -
> -/* defines the operations required for secure state transition */
> -#define DPU_KMS_OPS_CRTC_SECURE_STATE_CHANGE BIT(0)
> -#define DPU_KMS_OPS_WAIT_FOR_TX_DONE BIT(1)
> -#define DPU_KMS_OPS_CLEANUP_PLANE_FB BIT(2)
> -#define DPU_KMS_OPS_PREPARE_PLANE_FB BIT(3)
> -
> /*
> * struct dpu_irq_callback - IRQ callback handlers
> * @list: list to callback
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index cbda7dbf8725..834dcc0bfefd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -839,8 +839,7 @@ int dpu_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
> }
>
> /**
> - * _dpu_plane_get_aspace: gets the address space based on the
> - * fb_translation mode property
> + * _dpu_plane_get_aspace: gets the address space
> */
> static int _dpu_plane_get_aspace(
> struct dpu_plane *pdpu,
> @@ -1823,13 +1822,6 @@ static int dpu_plane_rot_submit_command(struct drm_plane *plane,
> rot_cmd->rot90 = rstate->rot90;
> rot_cmd->hflip = rstate->hflip;
> rot_cmd->vflip = rstate->vflip;
> - fb_mode = dpu_plane_get_property(pstate,
> - PLANE_PROP_FB_TRANSLATION_MODE);
> - if ((fb_mode == DPU_DRM_FB_SEC) ||
> - (fb_mode == DPU_DRM_FB_SEC_DIR_TRANS))
> - rot_cmd->secure = true;
> - else
> - rot_cmd->secure = false;
>
> rot_cmd->prefill_bw = dpu_crtc_get_property(dpu_cstate,
> CRTC_PROP_ROT_PREFILL_BW);
> @@ -1910,7 +1902,6 @@ static int dpu_plane_rot_submit_command(struct drm_plane *plane,
> rstate->out_rotation = rstate->in_rotation;
> rstate->out_fb_flags = rot_cmd->dst_modifier ?
> DRM_MODE_FB_MODIFIERS : 0;
> - rstate->out_fb_flags |= rot_cmd->secure ? DRM_MODE_FB_SECURE : 0;
> rstate->out_fb_format = rot_cmd->dst_format;
> rstate->out_fb_pixel_format = rot_cmd->dst_pixel_format;
>
> @@ -3337,9 +3328,6 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
> case PLANE_PROP_BLEND_OP:
> /* no special action required */
> break;
> - case PLANE_PROP_FB_TRANSLATION_MODE:
> - pstate->dirty |= DPU_PLANE_DIRTY_FB_TRANSLATION_MODE;
> - break;
> case PLANE_PROP_PREFILL_SIZE:
> case PLANE_PROP_PREFILL_TIME:
> pstate->dirty |= DPU_PLANE_DIRTY_PERF;
> @@ -3387,21 +3375,6 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
> pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
> _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
>
> - /* update secure session flag */
> - if (pstate->dirty & DPU_PLANE_DIRTY_FB_TRANSLATION_MODE) {
> - bool enable = false;
> - int mode = dpu_plane_get_property(pstate,
> - PLANE_PROP_FB_TRANSLATION_MODE);
> -
> - if ((mode == DPU_DRM_FB_SEC) ||
> - (mode == DPU_DRM_FB_SEC_DIR_TRANS))
> - enable = true;
> - /* update secure session flag */
> - pdpu->pipe_hw->ops.setup_secure_address(pdpu->pipe_hw,
> - pstate->multirect_index,
> - enable);
> - }
> -
> /* update roi config */
> if (pstate->dirty & DPU_PLANE_DIRTY_RECTS) {
> POPULATE_RECT(&src, rstate->out_src_x, rstate->out_src_y,
> @@ -3683,12 +3656,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane,
> static const struct drm_prop_enum_list e_src_config[] = {
> {DPU_DRM_DEINTERLACE, "deinterlace"}
> };
> - static const struct drm_prop_enum_list e_fb_translation_mode[] = {
> - {DPU_DRM_FB_NON_SEC, "non_sec"},
> - {DPU_DRM_FB_SEC, "sec"},
> - {DPU_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
> - {DPU_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
> - };
> const struct dpu_format_extended *format_list;
> struct dpu_kms_info *info;
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> @@ -3890,12 +3857,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane,
> msm_property_install_blob(&pdpu->property_info, feature_name, 0,
> PLANE_PROP_FOLIAGE_COLOR);
> }
> -
> - msm_property_install_enum(&pdpu->property_info, "fb_translation_mode",
> - 0x0,
> - 0, e_fb_translation_mode,
> - ARRAY_SIZE(e_fb_translation_mode),
> - PLANE_PROP_FB_TRANSLATION_MODE);
> }
>
> static inline void _dpu_plane_set_csc_v1(struct dpu_plane *pdpu, void *usr_ptr)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index 717dfe05c6ee..ad9d5cf048b1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -94,7 +94,6 @@ struct dpu_plane_rot_state {
> #define DPU_PLANE_DIRTY_FORMAT 0x2
> #define DPU_PLANE_DIRTY_SHARPEN 0x4
> #define DPU_PLANE_DIRTY_PERF 0x8
> -#define DPU_PLANE_DIRTY_FB_TRANSLATION_MODE 0x10
> #define DPU_PLANE_DIRTY_ALL 0xFFFFFFFF
>
> /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c
> index d4b844979c4c..0bb07ee0bcf2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c
> @@ -319,10 +319,6 @@ int dpu_wb_connector_post_init(struct drm_connector *connector,
> struct dpu_connector *c_conn;
> struct dpu_wb_device *wb_dev = display;
> const struct dpu_format_extended *format_list;
> - static const struct drm_prop_enum_list e_fb_translation_mode[] = {
> - {DPU_DRM_FB_NON_SEC, "non_sec"},
> - {DPU_DRM_FB_SEC, "sec"},
> - };
>
> if (!connector || !info || !display || !wb_dev->wb_cfg) {
> DPU_ERROR("invalid params\n");
> @@ -347,12 +343,6 @@ int dpu_wb_connector_post_init(struct drm_connector *connector,
> 0x0, 0, UINT_MAX, 0, CONNECTOR_PROP_DST_W);
> msm_property_install_range(&c_conn->property_info, "DST_H",
> 0x0, 0, UINT_MAX, 0, CONNECTOR_PROP_DST_H);
> - msm_property_install_enum(&c_conn->property_info,
> - "fb_translation_mode",
> - 0x0,
> - 0, e_fb_translation_mode,
> - ARRAY_SIZE(e_fb_translation_mode),
> - CONNECTOR_PROP_FB_TRANSLATION_MODE);
>
> /*
> * Populate info buffer
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 2c93d74ca973..cf96a85f4b55 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -116,7 +116,6 @@ enum msm_mdp_plane_property {
> PLANE_PROP_ROTATION,
> PLANE_PROP_BLEND_OP,
> PLANE_PROP_SRC_CONFIG,
> - PLANE_PROP_FB_TRANSLATION_MODE,
>
> /* total # of properties */
> PLANE_PROP_COUNT
> @@ -146,7 +145,6 @@ enum msm_mdp_crtc_property {
> CRTC_PROP_ROT_PREFILL_BW,
> CRTC_PROP_ROT_CLK,
> CRTC_PROP_ROI_V1,
> - CRTC_PROP_SECURITY_LEVEL,
> CRTC_PROP_IDLE_TIMEOUT,
> CRTC_PROP_DEST_SCALER,
>
> @@ -179,7 +177,6 @@ enum msm_mdp_conn_property {
> CONNECTOR_PROP_TOPOLOGY_CONTROL,
> CONNECTOR_PROP_AUTOREFRESH,
> CONNECTOR_PROP_LP,
> - CONNECTOR_PROP_FB_TRANSLATION_MODE,
>
> /* total # of properties */
> CONNECTOR_PROP_COUNT
> diff --git a/include/uapi/drm/dpu_drm.h b/include/uapi/drm/dpu_drm.h
> index 826bf7b54896..da73279a5086 100644
> --- a/include/uapi/drm/dpu_drm.h
> +++ b/include/uapi/drm/dpu_drm.h
> @@ -66,48 +66,6 @@
> /* DRM bitmasks are restricted to 0..63 */
> #define DPU_DRM_BITMASK_COUNT 64
>
> -/**
> - * Framebuffer modes for "fb_translation_mode" PLANE and CONNECTOR property
> - *
> - * @DPU_DRM_FB_NON_SEC: IOMMU configuration for this framebuffer mode
> - * is non-secure domain and requires
> - * both stage I and stage II translations when
> - * this buffer is accessed by the display HW.
> - * This is the default mode of all frambuffers.
> - * @DPU_DRM_FB_SEC: IOMMU configuration for this framebuffer mode
> - * is secure domain and requires
> - * both stage I and stage II translations when
> - * this buffer is accessed by the display HW.
> - * @DPU_DRM_FB_NON_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode
> - * is non-secure domain and requires
> - * only stage II translation when
> - * this buffer is accessed by the display HW.
> - * @DPU_DRM_FB_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode
> - * is secure domain and requires
> - * only stage II translation when
> - * this buffer is accessed by the display HW.
> - */
> -
> -#define DPU_DRM_FB_NON_SEC 0
> -#define DPU_DRM_FB_SEC 1
> -#define DPU_DRM_FB_NON_SEC_DIR_TRANS 2
> -#define DPU_DRM_FB_SEC_DIR_TRANS 3
> -
> -/**
> - * Secure levels for "security_level" CRTC property.
> - * CRTC property which specifies what plane types
> - * can be attached to this CRTC. Plane component
> - * derives the plane type based on the FB_MODE.
> - * @ DPU_DRM_SEC_NON_SEC: Both Secure and non-secure plane types can be
> - * attached to this CRTC. This is the default state of
> - * the CRTC.
> - * @ DPU_DRM_SEC_ONLY: Only secure planes can be added to this CRTC. If a
> - * CRTC is instructed to be in this mode it follows the
> - * platform dependent restrictions.
> - */
> -#define DPU_DRM_SEC_NON_SEC 0
> -#define DPU_DRM_SEC_ONLY 1
> -
> /**
> * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
> * @num_ext_pxls_lr: Number of total horizontal pixels
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 8668925b5c25..eb7587a47cb6 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -443,7 +443,6 @@ struct drm_mode_fb_cmd {
>
> #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
> #define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
> -#define DRM_MODE_FB_SECURE (1<<2) /* for secure framebuffers */
>
> struct drm_mode_fb_cmd2 {
> __u32 fb_id;
> --
> 2.16.1.291.g4437f3f132-goog
>
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