On Thu, 2018-01-25 at 17:13 -0800, Stephen Boyd wrote:
> Some qcom platforms make some GPIOs or pins unavailable for use
> by non-secure operating systems, and thus reading or writing the
> registers for those pins will cause access control issues. Add
> support for a DT property to describe the set of GPIOs that are
> available for use so that higher level OSes are able to know what
> pins to avoid reading/writing.
>
> For now, we plumb this into the gpiochip irq APIs so that
> GPIO/pinctrl drivers can use the gpiochip_irqchip_irq_valid() to
> test validity of GPIOs.
> +static void of_gpiochip_init_irq_valid_mask(struct gpio_chip *chip)
> +{
> + int len, i;
> + u32 start, count;
> + struct device_node *np = chip->of_node;
Perhaps reversed tree style? (In the following function as well)
> + len = of_property_count_u32_elems(np, "reserved-gpio-
> ranges");
>
> + for (i = 0; i < len; i += 2) {
> + of_property_read_u32_index(np, "reserved-gpio-
> ranges",
> + i, &start);
> + of_property_read_u32_index(np, "reserved-gpio-
> ranges",
> + i + 1, &count);
of_find_property() + of_prop_next_u32() ?
> + if (size > 0 && size % 2 == 0)
> + gpiochip->irq.need_valid_mask = true;
ffs(size) >= 2 ?
--
Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Intel Finland Oy
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