Some 5xx based chipsets have different bins for GPU clock speeds.
Read the fuses (if applicable) and set the appropriate OPP table.
This will only work with OPP v2 tables - the bin will be ignored
for legacy pwrlevel tables.
Signed-off-by: Jordan Crouse <jcrouse@xxxxxxxxxxxxxx>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index a1f4eee..fdbe9e9 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -17,6 +17,8 @@
#include <linux/dma-mapping.h>
#include <linux/of_address.h>
#include <linux/soc/qcom/mdt_loader.h>
+#include <linux/pm_opp.h>
+#include <linux/nvmem-consumer.h>
#include "msm_gem.h"
#include "msm_mmu.h"
#include "a5xx_gpu.h"
@@ -1184,6 +1186,25 @@ static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu)
.get_timestamp = a5xx_get_timestamp,
};
+static void check_speed_bin(struct device *dev)
+{
+ struct nvmem_cell *cell;
+ u32 bin, val;
+
+ cell = nvmem_cell_get(dev, "speed_bin");
+
+ /* If a nvmem cell isn't defined, nothing to do */
+ if (IS_ERR(cell))
+ return;
+
+ bin = *((u32 *) nvmem_cell_read(cell, NULL));
+ nvmem_cell_put(cell);
+
+ val = (1 << bin);
+
+ dev_pm_opp_set_supported_hw(dev, &val, 1);
+}
+
struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
{
struct msm_drm_private *priv = dev->dev_private;
@@ -1210,6 +1231,8 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
a5xx_gpu->lm_leakage = 0x4E001A;
+ check_speed_bin(&pdev->dev);
+
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 4);
if (ret) {
a5xx_destroy(&(a5xx_gpu->base.base));
--
1.9.1
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