Re: [PATCH 10/10] drm/msm/dsi: Add PHY/PLL for 8x96

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On 01/20/2017 01:47 AM, Stephen Boyd wrote:
On 01/07, Archit Taneja wrote:
+
+static struct clk *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
+					     const char *name,
+					     const char *parent_name,
+					     unsigned long flags,
+					     u8 shift)
+{
+	struct dsi_pll_14nm_postdiv *pll_postdiv;
+	struct device *dev = &pll_14nm->pdev->dev;
+	struct clk_init_data postdiv_init = {
+		.parent_names = (const char *[]) { parent_name },
+		.num_parents = 1,
+		.name = name,
+		.flags = flags,
+		.ops = &clk_ops_dsi_pll_14nm_postdiv,
+	};
+
+	pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL);
+	if (!pll_postdiv)
+		return ERR_PTR(-ENOMEM);
+
+	pll_postdiv->pll = pll_14nm;
+	pll_postdiv->shift = shift;
+	/* both N1 and N2 postdividers are 4 bits wide */
+	pll_postdiv->width = 4;
+	/* range of each divider is from 1 to 15 */
+	pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
+	pll_postdiv->hw.init = &postdiv_init;
+
+	return clk_register(dev, &pll_postdiv->hw);

Can you use clk_hw_register() and the variants instead? Same for
the clk_provider calls in this patch.

Will do.

Thanks,
Archit


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