[PATCH v4 07/10] remoteproc: qcom: Add new routine for mss restart programming

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MSS restart is done via reset controller, but on certain hexagon
version clock reset controller interface can not be utilized as
MSS restart register is not a block control reset which are
supported via clock reset control framework. In this case
restart register is programmed directly by register programming
through ioremap.

Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@xxxxxxxxxxxxxx>
---
 .../devicetree/bindings/remoteproc/qcom,q6v5.txt   |  4 +++
 drivers/remoteproc/qcom_q6v5_pil.c                 | 35 ++++++++++++++++++----
 2 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index cbc165c..717bd4a 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -79,6 +79,10 @@ on the Qualcomm Hexagon core.
 	Definition: a phandle reference to a syscon representing TCSR followed
 		    by the three offsets within syscon for q6, modem and nc
 		    halt registers.
+- qcom,qdsp6v56-1-5:
+	Usage: required
+	Value type: boolean
+	Definition: Present if the qdsp version is v56 1.5
 
 = SUBNODES:
 The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
index fe7c409..77a69eb 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -148,6 +148,8 @@ struct q6v5 {
 	phys_addr_t mpss_reloc;
 	void *mpss_region;
 	size_t mpss_size;
+
+	bool qdsp6v56_1_5;
 };
 
 
@@ -335,6 +337,14 @@ static void q6v5_clk_disable(struct q6v5 *qproc)
 	q6v5_active_clk_disable(qproc);
 }
 
+static void pil_mss_restart_reg(struct q6v5 *qproc, u32 mss_restart)
+{
+	if (qproc->restart_reg) {
+		writel_relaxed(mss_restart, qproc->restart_reg);
+		udelay(2);
+	}
+}
+
 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 {
 	struct q6v5 *qproc = rproc->priv;
@@ -644,10 +654,15 @@ static int q6v5_start(struct rproc *rproc)
 		dev_err(qproc->dev, "failed to enable supplies\n");
 		goto disable_proxy_clk;
 	}
-	ret = reset_control_deassert(qproc->mss_restart);
-	if (ret) {
-		dev_err(qproc->dev, "failed to deassert mss restart\n");
+
+	if (qproc->qdsp6v56_1_5)
+		pil_mss_restart_reg(qproc, 0);
+	else {
+		ret = reset_control_deassert(qproc->mss_restart);
+		if (ret) {
+			dev_err(qproc->dev, "failed to deassert mss restart\n");
 		goto disable_vdd;
+		}
 	}
 
 	ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
@@ -700,7 +715,8 @@ static int q6v5_start(struct rproc *rproc)
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 	q6v5_active_clk_disable(qproc);
 assert_reset:
-	reset_control_assert(qproc->mss_restart);
+	if (qproc->qdsp6v56_1_5)
+		reset_control_assert(qproc->mss_restart);
 disable_vdd:
 	q6v5_active_regulator_disable(qproc);
 disable_proxy_clk:
@@ -731,7 +747,13 @@ static int q6v5_stop(struct rproc *rproc)
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 	q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 
-	reset_control_assert(qproc->mss_restart);
+	if (qproc->qdsp6v56_1_5)
+		pil_mss_restart_reg(qproc, 1);
+	else {
+		ret = reset_control_assert(qproc->mss_restart);
+		if (ret)
+			dev_err(qproc->dev, "failed to deassert mss restart\n");
+	}
 	q6v5_clk_disable(qproc);
 	q6v5_regulator_disable(qproc);
 
@@ -1063,6 +1085,9 @@ static int q6v5_probe(struct platform_device *pdev)
 	}
 	qproc->active_reg_count = count;
 
+	qproc->qdsp6v56_1_5 = of_property_read_bool(pdev->dev.of_node,
+						"qcom,qdsp6v56-1-5");
+
 	ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
 	if (ret < 0)
 		goto free_rproc;
-- 
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.

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