The DSI/HDMI PLLs in MSM require resources like interface clocks, power
domains to be enabled before we can access their registers.
The clock framework doesn't have a mechanism at the moment where we can
tie such resources to a clock, so we make sure that the KMS driver enables
these resources whenever a PLL is expected to be in use.
One place where we can't ensure the resource dependencies are met is when
the clock framework tries to disable unused clocks. The KMS driver doesn't
know when the clock framework calls the is_enabled clk_op, and hence can't
enable interface clocks/power domains beforehand.
We remove the is_enabled clk_ops from the PLL clocks for now since they
aren't mandatory. This needs to be revisited, since bootloaders can enable
display, the enable count maintained by clock framework wouldn't work in
such cases.
Cc: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
Signed-off-by: Archit Taneja <architt@xxxxxxxxxxxxxx>
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 10 ----------
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 10 ----------
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 13 -------------
3 files changed, 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
index 598fdaf..80b7fc3 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
@@ -248,15 +248,6 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
-static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
-{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
-
- return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
- POLL_TIMEOUT_US);
-}
-
static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -312,7 +303,6 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
.prepare = msm_dsi_pll_helper_clk_prepare,
.unprepare = msm_dsi_pll_helper_clk_unprepare,
- .is_enabled = dsi_pll_28nm_clk_is_enabled,
};
/*
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
index 38c90e1..b3d3ec7 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
@@ -156,15 +156,6 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
-static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
-{
- struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
- struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
-
- return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
- POLL_TIMEOUT_US);
-}
-
static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -206,7 +197,6 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
.prepare = msm_dsi_pll_helper_clk_prepare,
.unprepare = msm_dsi_pll_helper_clk_unprepare,
- .is_enabled = dsi_pll_28nm_clk_is_enabled,
};
/*
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
index aa94a55..f3334e8 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
@@ -672,25 +672,12 @@ static void hdmi_8996_pll_unprepare(struct clk_hw *hw)
{
}
-static int hdmi_8996_pll_is_enabled(struct clk_hw *hw)
-{
- struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
- u32 status;
- int pll_locked;
-
- status = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS);
- pll_locked = status & BIT(0);
-
- return pll_locked;
-}
-
static struct clk_ops hdmi_8996_pll_ops = {
.set_rate = hdmi_8996_pll_set_clk_rate,
.round_rate = hdmi_8996_pll_round_rate,
.recalc_rate = hdmi_8996_pll_recalc_rate,
.prepare = hdmi_8996_pll_prepare,
.unprepare = hdmi_8996_pll_unprepare,
- .is_enabled = hdmi_8996_pll_is_enabled,
};
static const char * const hdmi_pll_parents[] = {
--
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