With the venus subcore0/1 gdscs(powerdomains) in
hw controlled mode, the clock controller does not handle
the status bit for the clocks in that domain. So avoid
checking for the status bit of those clocks by setting the
BRANCH_HALT_DELAY flag. This avoids the WARN_ONs which
otherwise occurs when enabling/disabling those clocks.
Signed-off-by: Sricharan R <sricharan@xxxxxxxxxxxxxx>
---
drivers/clk/qcom/mmcc-msm8996.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 41aabe3..8f3f480 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -1760,6 +1760,7 @@ enum {
};
static struct clk_branch video_subcore0_clk = {
+ .halt_check = BRANCH_HALT_DELAY,
.halt_reg = 0x1048,
.clkr = {
.enable_reg = 0x1048,
@@ -1775,6 +1776,7 @@ enum {
};
static struct clk_branch video_subcore1_clk = {
+ .halt_check = BRANCH_HALT_DELAY,
.halt_reg = 0x104c,
.clkr = {
.enable_reg = 0x104c,
--
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