On 16/09/16 14:52, Rob Herring wrote:
On Wed, Sep 07, 2016 at 11:55:32AM +0100, Srinivas Kandagatla wrote:
This patch adds bindings for pcie phy on MSM8996.
This PHY has 3 Ports, including a common block. Each port is connected
to one root complex. Each port has dedicated reset control lines apart
from common reset and clocks for common block.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
---
.../bindings/phy/qcom-msm8996-pcie-phy.txt | 62 ++++++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt b/Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt
new file mode 100644
index 0000000..51930ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-msm8996-pcie-phy.txt
@@ -0,0 +1,62 @@
+Qualcomm msm8996 pcie PHY
+------------------------
+
+Required properties:
+- compatible: compatible list, contains "qcom,msm8996-pcie-phy".
8994 has PCIe, this phy is completely different? And Archit mentioned
another SoC, too.
Recently I too learned that this phy IP is used across USB, UFS and
other SOCs, so Am planning to dump this patchset and write one common
driver.
Thanks,
srini
Rob
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