Add support to dump UFS MCQ registers to enhance debugging capabilities
for the Qualcomm UFS Host Controller.
Signed-off-by: Manish Pandey <quic_mapa@xxxxxxxxxxx>
---
drivers/ufs/host/ufs-qcom.c | 60 +++++++++++++++++++++++++++++++++++++
drivers/ufs/host/ufs-qcom.h | 2 ++
2 files changed, 62 insertions(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 028833acb3db..fc9e8d0ddc92 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1542,6 +1542,54 @@ int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
return 0;
}
+static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba)
+{
+ /* sleep intermittently to prevent CPU hog during data dumps. */
+ /* RES_MCQ_1 */
+ ufshcd_dump_regs(hba, 0x0, 256 * 4, "MCQ HCI 1da0000-1da03f0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_2 */
+ ufshcd_dump_regs(hba, 0x400, 256 * 4, "MCQ HCI 1da0400-1da07f0 ");
+ usleep_range(1000, 1100);
+
+ /*RES_MCQ_VS */
+ ufshcd_dump_regs(hba, 0x0, 5 * 4, "MCQ VS 1da4000-1da4010 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_1 */
+ ufshcd_dump_regs(hba, 0x0, 256 * 4, "MCQ SQD 1da5000-1da53f0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_2 */
+ ufshcd_dump_regs(hba, 0x400, 256 * 4, "MCQ SQD 1da5400-1da57f0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_3 */
+ ufshcd_dump_regs(hba, 0x800, 256 * 4, "MCQ SQD 1da5800-1da5bf0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_4 */
+ ufshcd_dump_regs(hba, 0xc00, 256 * 4, "MCQ SQD 1da5c00-1da5ff0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_5 */
+ ufshcd_dump_regs(hba, 0x1000, 256 * 4, "MCQ SQD 1da6000-1da63f0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_6 */
+ ufshcd_dump_regs(hba, 0x1400, 256 * 4, "MCQ SQD 1da6400-1da67f0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_7 */
+ ufshcd_dump_regs(hba, 0x1800, 256 * 4, "MCQ SQD 1da6800-1da6bf0 ");
+ usleep_range(1000, 1100);
+
+ /* RES_MCQ_SQD_8 */
+ ufshcd_dump_regs(hba, 0x1c00, 256 * 4, "MCQ SQD 1da6c00-1da6ff0 ");
+ usleep_range(1000, 1100);
+}
+
static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
{
u32 reg;
@@ -1600,6 +1648,18 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
+
+ if (hba->mcq_enabled) {
+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ);
+ ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers ");
+ }
+
+ /* ensure below dumps occur only in task context due to blocking calls. */
+ if (in_task()) {
+ /* Dump MCQ Host Vendor Specific Registers */
+ if (hba->mcq_enabled)
+ ufs_qcom_dump_mcq_hci_regs(hba);
+ }
}
/**
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index a5bf1282ddbe..6087fd1534b4 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -50,6 +50,8 @@ enum {
*/
UFS_AH8_CFG = 0xFC,
+ UFS_RD_REG_MCQ = 0xD00,
+
REG_UFS_CFG3 = 0x271C,
REG_UFS_DEBUG_SPARE_CFG = 0x284C,
--
2.17.1
