On 3/14/25 3:54 PM, Manivannan Sadhasivam wrote: > On Tue, Mar 11, 2025 at 01:29:15AM +0530, Vinod Koul wrote: >> On 10-03-25, 16:58, Wenbin Yao (Consultant) wrote: >>> On 2/26/2025 6:35 PM, Wenbin Yao wrote: >>>> The series aims to skip phy register programming and drive PCIe PHY with >>>> register setting programmed in bootloader by simply toggling no_csr reset, >>>> which once togglled, PHY hardware will be reset while PHY registers are >>>> retained. >>>> >>>> First, determine whether PHY setting can be skipped by checking >>>> QPHY_START_CTRL register and the existence of nocsr reset. If it is >>>> programmed and no_csr reset is supported, do no_csr reset and skip BCR >>>> reset which will reset entire PHY. >>>> >>>> This series also remove has_nocsr_reset flag in qmp_phy_cfg structure and >>>> decide whether the PHY supports nocsr reset by checking the existence of >>>> nocsr reset in device tree. >>>> >>>> The series are tested on X1E80100-QCP and HDK8550. >>>> >>>> The commit messages of this patchset have been modified based on comments >>>> and suggestions. >>>> >>>> Changes in v5: >>>> - Add a check whether the init sequences are exist if the PHY needs to be >>>> initialized to Patch 2/2. >>>> - Link to v4: https://lore.kernel.org/all/20250220102253.755116-1-quic_wenbyao@xxxxxxxxxxx/ >>>> >>>> Changes in v4: >>>> - Add Philipp's Reviewed-by tag to Patch 1/2. >>>> - Use PHY instead of phy in comments in Patch 2/2. >>>> - Use "if (qmp->nocsr_reset)" instead of "if (!qmp->nocsr_reset)" in >>>> function qmp_pcie_exit for readability in Patch 2/2. >>>> - Use goto statements in function qmp_pcie_power_on and qmp_pcie_power_off >>>> for readability in Patch 2/2. >>>> - Refine the comment of why not checking qmp->skip_init when reset PHY in >>>> function qmp_pcie_power_off in Patch 2/2. >>>> - Link to v3: https://lore.kernel.org/all/20250214104539.281846-1-quic_wenbyao@xxxxxxxxxxx/ >>>> >>>> Changes in v3: >>>> - Replace devm_reset_control_get_exclusive with >>>> devm_reset_control_get_optional_exclusive when get phy_nocsr reset >>>> control in Patch 1/2. >>>> - Do not ignore -EINVAL when get phy_nocsr reset control in Patch 1/2. >>>> - Replace phy_initialized with skip_init in struct qmp_pcie in Patch 2/2. >>>> - Add a comment to why not check qmp->skip_init in function >>>> qmp_pcie_power_off in Patch 2/2. >>>> - Link to v2: https://lore.kernel.org/all/20250211094231.1813558-1-quic_wenbyao@xxxxxxxxxxx/ >>>> >>>> Changes in v2: >>>> - Add Abel's and Manivannan's Reviewed-by tag to Patch 1/2. >>>> - Refine commit msg of Patch 2/2. >>>> - Link to v1: https://lore.kernel.org/all/20250121094140.4006801-1-quic_wenbyao@xxxxxxxxxxx/ >>>> >>>> Konrad Dybcio (1): >>>> phy: qcom: pcie: Determine has_nocsr_reset dynamically >>>> >>>> Qiang Yu (1): >>>> phy: qcom: qmp-pcie: Add PHY register retention support >>>> >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 86 +++++++++++++++++------- >>>> 1 file changed, 63 insertions(+), 23 deletions(-) >>>> >>>> >>>> base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7 >>> >>> Hi, do you have any futher comments? >> >> Patches lgtm, It would be great if this was tested by someone as well... >> Abel, Stephan, Neil can you folks test this and provide T-B >> > > I tested the previous version and it worked well on X1P40100-CRD. Will give this > version a go and give my tag. > >> I am also concerned about bootloader assumptions esp if the Qcom boot >> chain is skipped If any major part of this boot chain is skipped, much of the platform will unfortunately not behave as expected by the kernel today, anyway. While I personally enjoy hacking on such things, holding back hw support because of theoretical issues is not going to help here, especially since the tables can be trivially added at a later point, if ever needed, without requiring DT changes. > In that case, someone should add the PHY init sequence to the driver. That's why > I wanted to have the check in place to avoid silently failing PHY > initialization. Right now, the driver will error out if there is no init > sequence available. IIUC we internally settled on not sending the sequences for X1P4, since the PHYs are initialized as expected. Konrad
