The BAM block expects NAND register addresses to be computed based on
the NAND register offset from QPIC base. This value is 0x30000 for
ipq9574. Update the 'nandc_offset' value in the qcom_nandc_props
appropriately.
Signed-off-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx>
---
Change in [v3]
* Added nand_offset for proper address calculation
for newer Socs
Change in [v2]
* This patch was not part of v2
Change in [v1]
* This patch was not part of v1
drivers/spi/spi-qpic-snand.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
index 8c413a6a5152..85a742e21cf9 100644
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -1604,6 +1604,7 @@ static void qcom_spi_remove(struct platform_device *pdev)
static const struct qcom_nandc_props ipq9574_snandc_props = {
.dev_cmd_reg_start = 0x7000,
.supports_bam = true,
+ .nandc_offset = 0x30000,
};
static const struct of_device_id qcom_snandc_of_match[] = {
--
2.34.1
