On 3/4/2025 6:37 PM, Bryan O'Donoghue wrote: > From: Konrad Dybcio <konradybcio@xxxxxxxxxx> > > Both of these SoCs implement an IRIS2 block, with SC8280XP being able > to clock it a bit higher. > > Document it. > > Signed-off-by: Konrad Dybcio <konradybcio@xxxxxxxxxx> > Link: https://lore.kernel.org/r/20230731-topic-8280_venus-v1-1-8c8bbe1983a5@xxxxxxxxxx > Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx> > [ bod: dropped dts video-encoder/video-decoder ] > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx> > --- > .../bindings/media/qcom,sm8350-venus.yaml | 119 +++++++++++++++++++++ > 1 file changed, 119 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml > new file mode 100644 > index 0000000000000..352ad85ae50cd > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sm8350-venus.yaml > @@ -0,0 +1,119 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,sm8350-venus.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8350 Venus video encode and decode accelerators Again, what is the need to introduce a new bindings for sm8350 and how different is this with sm8250 ? > + > +maintainers: > + - Konrad Dybcio <konradybcio@xxxxxxxxxx> > + > +description: | > + The Venus Iris2 IP is a video encode and decode accelerator present > + on Qualcomm platforms > + > +allOf: > + - $ref: qcom,venus-common.yaml# > + > +properties: > + compatible: > + enum: > + - qcom,sc8280xp-venus > + - qcom,sm8350-venus > + > + clocks: > + maxItems: 3 > + > + clock-names: > + items: > + - const: iface > + - const: core > + - const: vcodec0_core > + > + resets: > + maxItems: 1 > + > + reset-names: > + items: > + - const: core > + > + power-domains: > + maxItems: 3 > + > + power-domain-names: > + items: > + - const: venus > + - const: vcodec0 > + - const: mx > + > + interconnects: > + maxItems: 3 > + > + interconnect-names: > + items: > + - const: cpu-cfg > + - const: video-mem > + - const: video-llcc > + > + operating-points-v2: true > + opp-table: > + type: object > + > + iommus: > + maxItems: 1 > + > +required: > + - compatible > + - power-domain-names > + - iommus > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/qcom,gcc-sm8350.h> > + #include <dt-bindings/clock/qcom,sm8350-videocc.h> > + #include <dt-bindings/interconnect/qcom,icc.h> > + #include <dt-bindings/interconnect/qcom,sm8350.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + venus: video-codec@aa00000 { > + compatible = "qcom,sm8350-venus"; > + reg = <0x0aa00000 0x100000>; > + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, > + <&videocc VIDEO_CC_MVS0C_CLK>, > + <&videocc VIDEO_CC_MVS0_CLK>; > + clock-names = "iface", > + "core", > + "vcodec0_core"; > + > + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; > + reset-names = "core"; > + > + power-domains = <&videocc MVS0C_GDSC>, > + <&videocc MVS0_GDSC>, > + <&rpmhpd SM8350_MX>; > + power-domain-names = "venus", > + "vcodec0", > + "mx"; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "cpu-cfg", > + "video-mem", > + "video-llcc"; > + > + operating-points-v2 = <&venus_opp_table>; > + iommus = <&apps_smmu 0x2100 0x400>; > + memory-region = <&pil_video_mem>; > + > + status = "disabled"; > + }; > Regards, Vikash
