On Wed, 29 Jan 2025 16:45:19 +0100, Krzysztof Kozlowski wrote:
> The parent of disp_cc_mdss_byte0_intf_clk clock should not propagate up
> the rates, because this messes up entire clock hierarchy when setting
> clock rates in MSM DSI driver.
>
> The dsi_link_clk_set_rate_6g() first sets entire clock hierarchy rates
> via dev_pm_opp_set_rate() on byte clock and then sets individual clock
> rates, like pixel and byte_intf clocks, to proper frequencies. Having
> CLK_SET_RATE_PARENT caused that entire tree was re-calced and the byte
> clock received halved frequency. Drop CLK_SET_RATE_PARENT to fix this
> and align with SM8550 and SM8650.
>
> [...]
Applied, thanks!
[1/1] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent
commit: 787289a1d13d50ff4ce0f496947f8817ef3fdea9
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
