On Fri, Feb 28, 2025 at 01:37:51AM +0530, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@xxxxxxxxxxx>
>
> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>
> Signed-off-by: Jie Zhang <quic_jiezh@xxxxxxxxxxx>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@xxxxxxxxxxx>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +-
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++
> 4 files changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 0ae29a7c8a4d3f74236a35cc919f69d5c0a384a0..1820c167fcee609deee3d49e7b5dd3736da23d99 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -616,6 +616,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> gpu->ubwc_config.uavflagprd_inv = 2;
> }
>
> + if (adreno_is_a623(gpu)) {
> + gpu->ubwc_config.highest_bank_bit = 16;
Just to doublecheck, the MDSS patch for QCS8300 used HBB=2, which
means 15. Is 16 correct here? Or might the be a mistake in the MDSS
patch?
> + gpu->ubwc_config.amsbc = 1;
> + gpu->ubwc_config.rgb565_predicator = 1;
> + gpu->ubwc_config.uavflagprd_inv = 2;
> + gpu->ubwc_config.macrotile_mode = 1;
> + }
> +
> if (adreno_is_a640_family(gpu))
> gpu->ubwc_config.amsbc = 1;
>
--
With best wishes
Dmitry
