On Wed, 29 Jan 2025 12:55:04 +0100, Krzysztof Kozlowski wrote:
> Since SM8250 all downstream sources program clock inverters in
> PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as
> reset value (0x0). The most recent Hardware Programming Guide for 3 nm,
> 4 nm, 5 nm and 7 nm PHYs also mention PLL_CLOCK_INVERTERS_1.
>
>
Applied, thanks!
[1/1] drm/msm/dsi/phy: Program clock inverters in correct register
https://gitlab.freedesktop.org/lumag/msm/-/commit/baf490728777
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
