On 2/26/2025 10:12 AM, Bjorn Andersson wrote: > On Thu, Feb 06, 2025 at 03:43:21PM +0530, Taniya Das wrote: >> Certain clocks are not accessible on QCM6490-IDP board, >> thus mark them as protected. >> >> Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx> >> --- >> Mark few clocks as protected on IDP of QCM6490. >> >> This patchset is separated out from the series[1] to remove dependency from >> the LPASS reset. >> [1]: https://lore.kernel.org/all/20240816-qcm6490-lpass-reset-v1-0-a11f33cad3c5@xxxxxxxxxxx/ >> --- >> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 21 +++++++++++++++++++++ > > I merged the patch adding this board in November 2023, are you saying > that for the last 15 months no one has actually booted it!? > I am not sure, I had got request to help boot the board which was not due to these clocks. >> 1 file changed, 21 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> index 9209efcc49b57a853c4dd55ac52cd4dc98d7fe86..346b9a377e611cd3e32cf00d44e87b363bada07a 100644 >> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> @@ -759,3 +759,24 @@ &wifi { >> >> status = "okay"; >> }; >> + >> +&gcc { > > As you know, we sort nodes by address (if they have one), then > alphabetically. So this does not belong here. > > Regards, > Bjorn > >> + protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, >> + <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, >> + <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, >> + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, >> + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, >> + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, >> + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, >> + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, >> + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, >> + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, >> + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, >> + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, >> + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, >> + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, >> + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, >> + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, >> + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, >> + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; >> +}; >> >> --- >> base-commit: 808eb958781e4ebb6e9c0962af2e856767e20f45 >> change-id: 20250206-protected_clock_qcm6490-4019e6a61d0b >> >> Best regards, >> -- >> Taniya Das <quic_tdas@xxxxxxxxxxx> >>
