Hey folks, In the vendor kernel, everything is handled in a single phy driver, with helpers for functions outside it. Clocks and regulators are specified and enabled in one node, which makes it difficult to separate what clocks and regulators go where without access to schematics or TRMs. The following gates are defined for USB: CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40 CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK The vendor kernel specifies 4 regulators, 2 of which are for eUSB and the other 2 for the repeater. The rest of the PHYs and the dwc3 controller are on a single power domain (hsi0), so they're most likely sharing power rails.
