On 19/02/2025 18:24, Dmitry Baryshkov wrote: > On Wed, 19 Feb 2025 at 19:04, Krzysztof Kozlowski > <krzysztof.kozlowski@xxxxxxxxxx> wrote: >> >> On 17/02/2025 20:18, Dmitry Baryshkov wrote: >>> On Mon, Feb 17, 2025 at 05:41:36PM +0100, Krzysztof Kozlowski wrote: >>>> Implement new features and differences coming in v12.0 of DPU present on >>>> Qualcomm SM8750 SoC: >>>> 1. 10-bit color alpha. >>>> 2. New CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers for pipes and >>>> layer mixers. >>>> 2. Several differences in LM registers (also changed offsets) for LM >>>> crossbar hardware changes. >>> >>> I'd really prefer for this patch to be split into a logical chunks >>> rather than "everything for 12.x" >> everything 12.x is still logical chunk. I can split more, but without >> guidance what is here logical chunk, will be tricky. >> >> For example 10-bit color alpha looks like separate feature. But >> remaining PIPE/LAYER active - not sure. >> >> I can split them but I would not call such split necessarily logical. > > I'd say, the following items are logical chunks: > - ctl->ops.active_fetch_pipes in dpu_encoder_helper_reset_mixers() and > dpu_hw_ctl_reset_intf_cfg_v1() (with a proper Fixes tag?) Ack > - 10-bit alpha, border color, Ack, > - active_pipes > - blend stage in LM + set_active_lms Ack, but you do understand that this is purely from new hardware, so new registers. Even the 10bit border color is actually for new registers. It makes no context outside of new hardware. same here. Best regards, Krzysztof
