On 08/11, Rajendra Nayak wrote:
> Some PLLs can support an alpha mode, and a single alpha
> register (instead of registers to program the M/N values),
> the contents of which depend on the alpha mode selected.
> (They are either treated as two's complement or M/N value)
That's just a sentence, so please drop the parentheses.
> Add support for this in the clk PLL driver.
>
I'm confused, don't we already have clk-alpha-pll.c to handle
alpha type plls? What are we doing adding support to the "legacy"
pll code?
> Signed-off-by: Rajendra Nayak <rnayak@xxxxxxxxxxxxxx>
> ---
> drivers/clk/qcom/clk-pll.c | 8 ++++++--
> drivers/clk/qcom/clk-pll.h | 2 ++
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
> index 5b940d6..08d2fa2 100644
> --- a/drivers/clk/qcom/clk-pll.c
> +++ b/drivers/clk/qcom/clk-pll.c
> @@ -255,8 +255,12 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
> u32 mask;
>
> regmap_write(regmap, pll->l_reg, config->l);
> - regmap_write(regmap, pll->m_reg, config->m);
> - regmap_write(regmap, pll->n_reg, config->n);
> + if (pll->alpha_reg) {
This assumes that alpha_reg is not 0 offset from base, which
seems like a bad assumption to make.
> + regmap_write(regmap, pll->alpha_reg, config->alpha);
> + } else {
> + regmap_write(regmap, pll->m_reg, config->m);
> + regmap_write(regmap, pll->n_reg, config->n);
> + }
>
> val = config->vco_val;
> val |= config->pre_div_val;
>
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