During boot-up, the PLL configuration might be missed even after calling pll_configure() from the clock controller probe. This can happen because the PLL is connected to one or more rails that are turned off, and the current clock controller code cannot enable multiple rails during probe. Consequently, the PLL may be activated with suboptimal settings, causing functional issues. The support to attach multiple power domains to clock controllers was recently added in Bryan's series[1] but it currently doesn't enable all clock controller power domains during probe which are needed for PLL configuration. This series adds required support to enable the multiple power domains during clock controllers probe and adds support to enable both MMCX & MXC rails during probe for videocc on SM8450, SM8475, SM8550 and SM8650 platforms to configure the video PLLs properly. This fixes the below warning reported in SM8550 venus testing due to video_cc_pll0 not properly getting configured during videocc probe [ 46.535132] Lucid PLL latch failed. Output may be unstable! [1]: https://lore.kernel.org/all/20250117-b4-linux-next-24-11-18-clock-multiple-power-domains-v10-0-13f2bb656dad@xxxxxxxxxx/ Signed-off-by: Jagadeesh Kona <quic_jkona@xxxxxxxxxxx> --- Jagadeesh Kona (4): dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain clk: qcom: common: Attach clock power domains conditionally clk: qcom: videocc: Add support to attach multiple power domains arm64: dts: qcom: Add MXC power domain to videocc nodes Taniya Das (1): clk: qcom: common: Add support to attach multiple power domains .../bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++--- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- drivers/clk/qcom/common.c | 21 ++++++++++++++++++--- drivers/clk/qcom/common.h | 2 ++ drivers/clk/qcom/videocc-sm8450.c | 4 ++++ drivers/clk/qcom/videocc-sm8550.c | 4 ++++ 8 files changed, 40 insertions(+), 9 deletions(-) --- base-commit: e5d3fd687aac5eceb1721fa92b9f49afcf4c3717 change-id: 20250218-videocc-pll-multi-pd-voting-d614dce910e7 Best regards, -- Jagadeesh Kona <quic_jkona@xxxxxxxxxxx>
