On 18.02.2025 4:11 AM, Dmitry Baryshkov wrote:
> On Mon, Feb 17, 2025 at 08:23:28PM +0100, Konrad Dybcio wrote:
>> On 17.02.2025 7:56 PM, Dmitry Baryshkov wrote:
>>> On the Qualcomm AR2 Gen1 platform the second PCIe host can be used
>>> either as an RC or as an EP device. Add device node for the PCIe EP.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
>>> ---
>>> arch/arm64/boot/dts/qcom/sar2130p.dtsi | 53 ++++++++++++++++++++++++++++++++++
>>> 1 file changed, 53 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
>>> index dd832e6816be85817fd1ecc853f8d4c800826bc4..7f007fad6eceebac1b2a863d9f85f2ce3dfb926a 100644
>>> --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
>>> @@ -1474,6 +1474,59 @@ pcie@0 {
>>> };
>>> };
>>>
>>> + pcie1_ep: pcie-ep@1c08000 {
>>> + compatible = "qcom,sar2130p-pcie-ep";
>>> + reg = <0x0 0x01c08000 0x0 0x3000>,
>>> + <0x0 0x40000000 0x0 0xf1d>,
>>> + <0x0 0x40000f20 0x0 0xa8>,
>>> + <0x0 0x40001000 0x0 0x1000>,
>>> + <0x0 0x40200000 0x0 0x1000000>,
>>> + <0x0 0x01c0b000 0x0 0x1000>,
>>> + <0x0 0x40002000 0x0 0x2000>;
>>> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
>>> + "mmio", "dma";
>>
>> vertical list, please
>
> Ack
>
>>
>>> +
>>> + clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
>>> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
>>> + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
>>> + <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
>>> + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
>>> + <&gcc GCC_DDRSS_PCIE_SF_CLK>,
>>> + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
>>> + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
>>> + <&gcc GCC_QMIP_PCIE_AHB_CLK>;
>>
>> please make sure this one is actually required
>
> Hmm, this one seems to be present in pcie0 and pcie1 RC, but in the EP
> deivice (in the vendor DT). Are you saying that it is not used for the
> EP? I think I just c&p'ed RC clocks here.
QMIP clocks did something special. I don't recall what clock ops are
translated to, but I suppose keeping them online makes sense..
>>
>>> + clock-names = "aux",
>>> + "cfg",
>>> + "bus_master",
>>> + "bus_slave",
>>> + "slave_q2a",
>>> + "ddrss_sf_tbu",
>>> + "aggre_noc_axi",
>>> + "cnoc_sf_axi",
>>> + "qmip_pcie_ahb";
>>> +
>>> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupt-names = "global", "doorbell", "dma";
>>
>> and here
>
> This is used for the eDMA implementation. Unlike the vendor kernel,
> there is no separate device for eDMA.
Sorry, I wrote this before looking at the clocks, I meant please make
interrupt-names a vertical list, too
Konrad
