On 12/5/2024 3:59 PM, Komal Bajaj wrote:
On 11/20/2024 5:29 PM, Dmitry Baryshkov wrote:
On Tue, Nov 19, 2024 at 12:16:08PM +0530, Komal Bajaj wrote:
The previous implementation incorrectly configured the
cmn_interrupt_2_enable
register for interrupt handling. Using cmn_interrupt_2_enable to
configure Tag,
Data RAM ECC interrupts would lead to issues like double handling of
the
interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be
configured
for interrupts which needs to be handled by EL3.
This reads as if it was possible to write EL3-related register from EL1.
Is it true?
Both EL1 and EL3 can access the LLCC "cmn_interrupt_2_enable"
register, but configuring the register from both
EL1 & EL3 shouldn't be done as the register is meant to be configured
from EL3. There was a bug in HPG which was
fixed recently on not to configure the register from EL1.
Thanks
Komal
Hi Dmitry,
Does this answer your query, or is there anything else you are looking for?
Thanks
Komal
EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to
configure Tag, Data RAM ECC interrupts instead of
cmn_interrupt_2_enable.
Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for
QCOM SoCs")
Signed-off-by: Komal Bajaj <quic_kbajaj@xxxxxxxxxxx>
---
drivers/edac/qcom_edac.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
index a9a8ba067007..0fd7a777fe7d 100644
--- a/drivers/edac/qcom_edac.c
+++ b/drivers/edac/qcom_edac.c
@@ -95,7 +95,7 @@ static int qcom_llcc_core_setup(struct
llcc_drv_data *drv, struct regmap *llcc_b
* Configure interrupt enable registers such that Tag, Data
RAM related
* interrupts are propagated to interrupt controller for
servicing
*/
- ret = regmap_update_bits(llcc_bcast_regmap,
drv->edac_reg_offset->cmn_interrupt_2_enable,
+ ret = regmap_update_bits(llcc_bcast_regmap,
drv->edac_reg_offset->cmn_interrupt_0_enable,
TRP0_INTERRUPT_ENABLE,
TRP0_INTERRUPT_ENABLE);
if (ret)
@@ -113,7 +113,7 @@ static int qcom_llcc_core_setup(struct
llcc_drv_data *drv, struct regmap *llcc_b
if (ret)
return ret;
- ret = regmap_update_bits(llcc_bcast_regmap,
drv->edac_reg_offset->cmn_interrupt_2_enable,
+ ret = regmap_update_bits(llcc_bcast_regmap,
drv->edac_reg_offset->cmn_interrupt_0_enable,
DRP0_INTERRUPT_ENABLE,
DRP0_INTERRUPT_ENABLE);
if (ret)
--
2.46.0
