On 12.02.2025 12:07 PM, Dmitry Baryshkov wrote: > On Wed, Feb 12, 2025 at 04:31:21PM +0800, Wenbin Yao (Consultant) wrote: >> On 2/12/2025 8:13 AM, Dmitry Baryshkov wrote: >>> On Tue, Feb 11, 2025 at 05:42:31PM +0800, Wenbin Yao wrote: >>>> From: Qiang Yu <quic_qianyu@xxxxxxxxxxx> >>>> >>>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the >>>> whole PHY (hardware and register), no_csr reset only resets PHY hardware >>>> but retains register values, which means PHY setting can be skipped during >>>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled >>>> after that. >>>> >>>> Hence, determine whether the PHY has been enabled in bootloader by >>>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is >>>> available, skip BCR reset and PHY register setting to establish the PCIe >>>> link with bootloader - programmed PHY settings. >>>> >>>> Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx> >>>> Signed-off-by: Wenbin Yao <quic_wenbyao@xxxxxxxxxxx> >>>> --- >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 91 +++++++++++++++--------- >>>> 1 file changed, 58 insertions(+), 33 deletions(-) >>>> > >>>> @@ -4042,16 +4057,22 @@ static int qmp_pcie_power_on(struct phy *phy) >>>> unsigned int mask, val; >>>> int ret; >>>> - qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], >>>> - cfg->pwrdn_ctrl); >>>> + /* >>>> + * Write CSR register for phy that doesn't support no_csr >>> what is CSR register? >> The registers of PHY. > > So 'CSR registers for phy' means 'registers of PHY for phy'? that seems > incorrect. "Control and Status Registers" Konrad
