Support mst for qcs8300 and add the stream 1 clock support in the mdss
dt-bindings.
Signed-off-by: Yongxing Mou <quic_yongmou@xxxxxxxxxxx>
---
.../devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
index eb7f36387f748793ebf662baded4a13a61b3ce39..610742ceebf8ee5e140a409bfeb92d9f43085214 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
@@ -53,7 +53,6 @@ patternProperties:
compatible:
items:
- const: qcom,qcs8300-dp
- - const: qcom,sm8650-dp
required:
- compatible
@@ -164,7 +163,7 @@ examples:
};
displayport-controller@af54000 {
- compatible = "qcom,qcs8300-dp", "qcom,sm8650-dp";
+ compatible = "qcom,qcs8300-dp";
pinctrl-0 = <&dp_hot_plug_det>;
pinctrl-names = "default";
@@ -181,15 +180,18 @@ examples:
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>, <&mdss_edp_phy 1>;
phys = <&mdss_edp_phy>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
--
2.34.1
