Add the OSM L3 controller node then add the necessary interconnect properties with the appropriate OPP table for each CPU cluster to allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU cluster operating point. Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> --- Changes in v2: - Drop already applied bindings patch - Link to v1: https://lore.kernel.org/r/20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@xxxxxxxxxx --- Neil Armstrong (3): arm64: dts: qcom: sm8650: add OSM L3 node arm64: dts: qcom: sm8650: add cpu interconnect nodes arm64: dts: qcom: sm8650: add cpu OPP table with DDR, LLCC & L3 bandwidths arch/arm64/boot/dts/qcom/sm8650.dtsi | 943 +++++++++++++++++++++++++++++++++++ 1 file changed, 943 insertions(+) --- base-commit: 808eb958781e4ebb6e9c0962af2e856767e20f45 change-id: 20250110-topic-sm8650-ddr-bw-scaling-f1863fb91246 Best regards, -- Neil Armstrong <neil.armstrong@xxxxxxxxxx>
