On 06/02/2025 19:46, Abhinav Kumar wrote:
Widebus allows the DP controller to operate in 2 pixel per clock mode.
The mode validation logic validates the mode->clock against the max
DP pixel clock. However the max DP pixel clock limit assumes widebus
is already enabled. Adjust the mode validation logic to only compare
the adjusted pixel clock which accounts for widebus against the max DP
pixel clock. Also fix the mode validation logic for YUV420 modes as in
that case as well, only half the pixel clock is needed.
Fixes: 757a2f36ab09 ("drm/msm/dp: enable widebus feature for display port")
Fixes: 6db6e5606576 ("drm/msm/dp: change clock related programming for YUV420 over DP")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Signed-off-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
Changes in v2:
- move msm_dp_wide_bus_available() to the next line
- Link to v1: https://lore.kernel.org/r/20250128-dp-widebus-fix-v1-1-b66d2265596b@xxxxxxxxxxx
---
drivers/gpu/drm/msm/dp/dp_display.c | 11 ++++++-----
drivers/gpu/drm/msm/dp/dp_drm.c | 5 ++++-
2 files changed, 10 insertions(+), 6 deletions(-)
This patch fixes a CLOCK_HIGH mode rejection error on the Microsoft
Surface Pro 11 (OLED panel) which I had previously been working-around
by raising DP_MAX_PIXEL_CLK_KHZ.
Tested-by: Dale Whinham <daleyo@xxxxxxxxx>
--
Best regards,
Dale
