On Thu, Jan 23, 2025 at 04:46:18PM +0530, Manikanta Mylavarapu wrote:
> The UART’s software and hardware flow control are currently not
> functioning correctly.
>
> For software flow control, the following error is encountered:
> qcom_geni_serial 1a80000.serial: Couldn't find suitable
> clock rate for 56000000, 3500000, 2500000, 1152000, 921600, 19200
>
> During hardware flow control testing, a “Retry 0: Got ZCAN error” is
> observed.
>
> To address these issues, update the UART frequency table to include all
> supported frequencies according to the frequency plan.
Would this need fixes tag?
-Varada
>
> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@xxxxxxxxxxx>
> ---
> drivers/clk/qcom/gcc-ipq5424.c | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c
> index d5b218b76e29..37b1a3ff8f4e 100644
> --- a/drivers/clk/qcom/gcc-ipq5424.c
> +++ b/drivers/clk/qcom/gcc-ipq5424.c
> @@ -592,13 +592,19 @@ static struct clk_rcg2 gcc_qupv3_spi1_clk_src = {
> };
>
> static const struct freq_tbl ftbl_gcc_qupv3_uart0_clk_src[] = {
> - F(960000, P_XO, 10, 2, 5),
> - F(4800000, P_XO, 5, 0, 0),
> - F(9600000, P_XO, 2, 4, 5),
> - F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
> + F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625),
> + F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625),
> + F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625),
> F(24000000, P_XO, 1, 0, 0),
> F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
> - F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
> + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
> + F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
> + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
> + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
> + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
> + F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
> + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
> F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
> { }
> };
>
> --
> 2.34.1
>
