MSM controller does not use the div, instead needs
the base clock and the driver controls the
base clock (MCLK) at GCC directly.
Signed-off-by: Sahitya Tummala <stummala@xxxxxxxxxxxxxx>
Signed-off-by: Ritesh Harjani <riteshh@xxxxxxxxxxxxxx>
---
drivers/mmc/host/sdhci-msm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index cfd0209..f148c96 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -570,6 +570,16 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
return msm_host->pdata->clk_table[0];
}
+/*
+ * MSM SDHC controller HW recomendation is to not use
+ * clock divisor hence return 0 from here.
+ * Driver directly controls the clk-rate at GCC.
+ */
+static int sdhci_msm_get_clk_div(struct sdhci_host *host, int div)
+{
+ return 0;
+}
+
static const struct of_device_id sdhci_msm_dt_match[] = {
{ .compatible = "qcom,sdhci-msm-v4" },
{},
@@ -586,6 +596,7 @@ static const struct sdhci_ops sdhci_msm_ops = {
.set_bus_width = sdhci_set_bus_width,
.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
.voltage_switch = sdhci_msm_voltage_switch,
+ .get_clk_div = sdhci_msm_get_clk_div,
};
static const struct sdhci_pltfm_data sdhci_msm_pdata = {
--
1.8.2.1
--
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