During boot-up, there is a possibility that the PLL configuration might be missed even after invoking pll_configure() from the clock controller probe. This is often due to the PLL being connected to rail or rails that are in an OFF state and current clock controller also cannot vote on multiple rails. As a result, the PLL may be enabled with suboptimal settings, leading to functional issues. The PLL configuration, now part of clk_alpha_pll, can be reused to reconfigure the PLL to a known good state before scaling for frequency. The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs in future. The IRIS driver support added https://lore.kernel.org/all/20241212-qcom-video-iris-v9-0-e8c2c6bd4041@xxxxxxxxxxx/ observes the pll latch warning during boot up due to the dependency of the PLL not in good state, thus add config support for SM8550 Video clock controller PLLs. Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx> --- Taniya Das (3): clk: qcom: clk-alpha-pll: Integrate PLL configuration into PLL structure clk: qcom: clk-alpha-pll: Add support to reconfigure PLL clk: qcom: videocc-sm8550: Update the pll config for Video PLLs drivers/clk/qcom/clk-alpha-pll.c | 30 ++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 2 ++ drivers/clk/qcom/videocc-sm8550.c | 2 ++ 3 files changed, 34 insertions(+) --- base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc change-id: 20250113-support-pll-reconfigure-9a9cbb43a90b Best regards, -- Taniya Das <quic_tdas@xxxxxxxxxxx>
