Add the OSM L3 controller node then add the necessary interconnect
properties with the appropriate OPP table for each CPU cluster to
allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
cluster operating point.
Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
---
Neil Armstrong (4):
dt-bindings: interconnect: OSM L3: Document sm8650 OSM L3 compatible
arm64: dts: qcom: sm8650: add OSM L3 node
arm64: dts: qcom: sm8650: add cpu interconnect nodes
arm64: dts: qcom: add cpu OPP table with DDR, LLCC & L3 bandwidths
.../bindings/interconnect/qcom,osm-l3.yaml | 1 +
arch/arm64/boot/dts/qcom/sm8650.dtsi | 938 +++++++++++++++++++++
2 files changed, 939 insertions(+)
---
base-commit: 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab
change-id: 20250110-topic-sm8650-ddr-bw-scaling-f1863fb91246
Best regards,
--
Neil Armstrong <neil.armstrong@xxxxxxxxxx>
