On Thu, Jan 09, 2025 at 02:08:38PM +0100, Krzysztof Kozlowski wrote:
> Not finished. Looking around, maybe someone already did some works
> around new CTL_PIPE_ACTIVE and CTL_LAYER_ACTIVE registers?
This is not enough, the whole blend setup is to be moved to LM
block.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 10 ++++++++--
> 4 files changed, 20 insertions(+), 8 deletions(-)
>
[...]
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 06b01cd36ce2442ee6e1b85be227851a234cc96b..502449cbbddcb21b7008f139ac065d187a16b68e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -40,6 +40,8 @@
> #define CTL_INTF_FLUSH 0x110
> #define CTL_CDM_FLUSH 0x114
> #define CTL_PERIPH_FLUSH 0x128
> +#define CTL_PIPE_ACTIVE 0x12C
> +#define CTL_LAYER_ACTIVE 0x130
> #define CTL_INTF_MASTER 0x134
> #define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4))
>
> @@ -729,8 +731,12 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
> ops->trigger_pending = dpu_hw_ctl_trigger_pending;
> ops->reset = dpu_hw_ctl_reset_control;
> ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
> - ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
> - ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
> + if (cap & BIT(DPU_CTL_NO_LAYER_EXT)) {
I'd prefer if this is was an explicit MDSS / DPU version check rather
than an extra feature bit, enable new functions for version >= 11.0
> + // TODO: NOT COMPLETE, This has to be implemented
> + } else {
> + ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
> + ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
> + }
> ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
> ops->update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
> if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
>
> --
> 2.43.0
>
--
With best wishes
Dmitry
