On 12/30/2024 6:49 PM, Konrad Dybcio wrote:
On 27.12.2024 12:00 PM, Pratyush Brahma wrote:
Add the device node for gfx smmu that is required for gpu
specific address translations.
This patch depends on the patch series [1] posted by Imran Shaik
adding the clock support for gpu.
[1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@xxxxxxxxxxxxxxxx/
Signed-off-by: Pratyush Brahma <quic_pbrahma@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 80226992a65d..8eb688e2df0a 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -816,6 +816,43 @@
#power-domain-cells = <1>;
};
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x3da0000 0x0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ dma-coherent;
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HUB_AON_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk";
Most of these entries look totally bogus, please make sure you only
reference the ones actually required
These entries are exactly similar to the ones we use in sa8775p as well
[1] and the usecases
haven't changed between qcs8300 and sa8775p.
Can you please let me know which entries you find irrelevant here?
[1] commit 1a1ff00c1626c "arm64: dts: qcom: sa8775p: add the GPU IOMMU node"
Konrad
--
Thanks and Regards
Pratyush Brahma
