Hi Bjorn,
On Fri, Jan 03, 2025 at 03:05:31PM -0600, Bjorn Helgaas wrote:
> On Thu, Mar 21, 2024 at 04:46:21PM +0530, Manivannan Sadhasivam wrote:
> > On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> > for each controller instance. Hence, add a node to represent the bridge.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 ++++++++++++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > index 39bd8f0eba1e..fe5485256b22 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > @@ -2203,6 +2203,16 @@ pcie0: pcie@1c00000 {
> > dma-coherent;
> >
> > status = "disabled";
> > +
> > + pcie@0 {
> > + device_type = "pci";
> > + reg = <0x0 0x0 0x0 0x0 0x0>;
> > + bus-range = <0x01 0xff>;
>
> Hi Mani, most or all of the patches in this series add this
> "bus-range" property. IIUC, these are all Root Ports and hence the
> secondary/subordinate bus numbers should be programmable.
>
Right. It is not a functional dependency.
> If that's the case, I don't think we need to include "bus-range" in DT
> for them, do we?
>
We mostly include it to silence the below bindings check for the endpoint device
node:
Warning (pci_device_bus_num): /soc@0/pcie@1c00000/pcie@0/wifi@0: PCI bus number 1 out of range, expected (0 - 0)
DTC check is happy if the 'bus-range' property is absent in the bridge node. But
while validating the endpoint node (if defined), it currently relies on the
parent 'bus-range' property to verify the bus number provided in the endpoint
'reg' property.
I don't know else the check can verify the correctness of the endpoint bus
number. So deferring to Rob here.
- Mani
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