On Wed, 19 Jul 2023 12:50:14 +0530, Krishna chaitanya chundru wrote:
> Add basic support for managing "pcie-mem" interconnect path by setting
> a low constraint before enabling clocks and updating it after the link
> is up based on link speed and width the device got enumerated.
>
> changes from v9:
> - addressed the comments by mani.
> changes from v8:
> - Added cpu to pcie path in dtsi and in dtsi binding.
> changes from v7:
> - setting icc bw to '0' in disable resources as suggested by mani.
> changes from v6:
> - addressed the comments as suggested by mani.
> changes from v5:
> - addressed the comments by mani.
> changes from v4:
> - rebased with linux-next.
> - Added comments as suggested by mani.
> - removed the arm: dts: qcom: sdx55: Add interconnect path
> as that patch is already applied.
> changes from v3:
> - ran make DT_CHECKER_FLAGS=-m dt_binding_check and fixed
> errors.
> - Added macros in the qcom ep driver patch as suggested by Dmitry
> changes from v2:
> - changed the logic for getting speed and width as suggested
> by bjorn.
> - fixed compilation errors.
>
> [...]
Applied, thanks!
[2/4] arm: dts: qcom: sdx65: Add PCIe EP interconnect path
commit: 84d2ae7c09d93949fc9e9fe57bdb78a2f3fa24aa
[3/4] arm: dts: qcom: sdx55: Add CPU PCIe EP interconnect path
commit: 7ec041bd2715df2da4ab19c403c27d58d173c7c0
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
