On 2024/12/6 5:36, Konrad Dybcio wrote:
On 27.11.2024 11:45 AM, Yongxing Mou wrote:
Add device tree nodes for the DPTX0 controller with their
corresponding PHYs found on Qualcomm QCS8300 SoC.
Signed-off-by: Yongxing Mou <quic_yongmou@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 {
interrupt-parent = <&mdss>;
interrupts = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
+ };
+ };
+ };
+
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -1011,6 +1024,104 @@ opp-650000000 {
};
};
};
+
+ mdss_dp0_phy: phy@aec2a00 {
+ compatible = "qcom,qcs8300-edp-phy";
+
+ reg = <0x0 0x0aec2a00 0x0 0x200>,
0x19c
got it.thanks.
+ <0x0 0x0aec2200 0x0 0xd0>,
0xec
got it.thanks.
+ <0x0 0x0aec2600 0x0 0xd0>,
0xec
For lengths
got it.thanks.
+ <0x0 0x0aec2000 0x0 0x1c8>;
This one's correct
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux",
+ "cfg_ahb";
power-domains = <&rpmhpd RPMHPD_MX>;
emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu..
(or maybe even MXC?)
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss_dp0: displayport-controller@af54000 {
+ compatible = "qcom,qcs8300-dp";
+
+ reg = <0x0 0x0af54000 0x0 0x104>,
0x200
got it. thanks.
+ <0x0 0x0af54200 0x0 0x0c0>,
0x200
got it. thanks.
+ <0x0 0x0af55000 0x0 0x770>,
0xc00
got it. thanks.
+ <0x0 0x0af56000 0x0 0x09c>;
0x400
will modify all the length in patch v2.
for lengths
Konrad
